The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.

An optoelectronic component includes a first housing body and a second housing body separate from the first housing body. A first section of a leadframe is embedded into the first housing body. A second section of the leadframe connected integrally the first section, is embedded into the second housing body.

Disclosed are apparatuses and methods for fabricating the apparatuses. In one aspect, an apparatus includes a high-power die mounted on a backside of a package substrate. A heat transfer layer is disposed on the backside of the high-power die. A plurality of heat sink interconnects is coupled to the heat transfer layer, where each of the plurality of heat sink interconnects is directly coupled to the heat transfer layer in a vertical orientation.

Disclosed are apparatuses and methods for fabricating the apparatuses. In one aspect, an apparatus includes a high-power die mounted on a backside of a package substrate. A heat transfer layer is disposed on the backside of the high-power die. A plurality of heat sink interconnects is coupled to the heat transfer layer. The plurality of heat sink interconnects is located adjacent the high-power die in a horizontal direction.

Flat no-leads integrated circuit (IC) packages are formed with solder wettable leadframe terminals. Dies are mounted on die attach pads, bonded to adjacent leadframe terminal structures, and encapsulated in a mold compound. A laser grooving process removes mold compound from a leadframe terminal groove extending along a row of leadframe terminal structures. A saw step cut along the leadframe terminal groove extends partially through the leadframe thickness to define a saw step cut groove. Exposed leadframe surfaces, including surfaces exposed by the saw step cut, are plated with a solder-enhancing material. A singulation cut is performed along the saw step cut groove to define leadframe terminals with end surfaces plated with the solder-enhancing material. The laser grooving process may improve the results of the saw step cut, and the saw step cut may remove mold compound not removed by the laser grooving process.

A method of using a processing oven may include disposing at least one substrate in a chamber of the oven and activating a lamp assembly disposed above them to increase their temperature to a first temperature. A chemical vapor may be admitted into the chamber above the at least one substrate and an inert gas may be admitted into the chamber below the at least one substrate. The temperature of the at least one substrate may then be increased to a second temperature higher than the first temperature and then cooled down.

A method of using a solder reflow oven can include disposing at least one substrate including solder in a chamber of the oven. The method can include decreasing a pressure of the chamber to a first pressure between about 0.1-50 Torr. After decreasing the pressure of the chamber, the temperature of the at least one substrate can be increased to a first temperature. Formic acid vapor can be admitted into the chamber above the at least one substrate while nitrogen is discharged into the chamber below the at least one substrate. The method can also include removing at least a portion of the formic acid vapor from the enclosure. After the removing step, the temperature of the at least one substrate can be further increased to a second temperature higher than the first temperature. The at least one substrate can be maintained at the second temperature for a first time. And then, the at least one substrate can be cooled.

A device package with a reduced foot print may include a substrate and a through-substrate via extending from a top surface to a bottom surface of the substrate. The assembly may also include a trace and a contact pad on the top and bottom surfaces of the substrate and electrically coupled to the through-substrate via. An encapsulated die above the substrate may be electrically coupled to the trace. A joint below the substrate may be electrically coupled to the contact pad. A sidewall of the through-substrate via may be exposed. At least a portion of the through-substrate via may be within an outer side boundary of the substrate. Also, the trace and the contact pad may be within the outer side boundary of the substrate.

The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor package. In one embodiment, a glass or silicon substrate is structured by micro-blasting or laser ablation to form structures for formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor package with embedded dies therein.

Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die. The connecting structure includes a plurality of via and groove combinations. Conductive material is formed in the via and groove combinations to provide connection between the die bond pads and bond pads on the support. Other embodiments are described and claimed.