A system and method for efficiently creating layout for memory bit cells are described. In various implementations, cells of a library use Cross field effect transistors (FETs) that include vertically stacked gate all around (GAA) transistors with conducting channels oriented in an orthogonal direction between them. The channels of the vertically stacked transistors use opposite doping polarities. A first category of cells includes devices where each of the two devices in a particular vertical stack receive a same input signal. The second category of cells includes devices where the two devices in a particular vertical stack receive different input signals. The cells of the second category have a larger height dimension than the cells of the first category.

A system and method for creating chip layout are described. In various implementations, a standard cell uses unidirectional tracks for power connections and signal routing. A single track of the metal one layer that uses a minimum width of the metal one layer is placed within a pitch of a single metal gate. The single track of the metal one layer provides a power supply reference voltage level or ground reference voltage level. This placement of the single track provides a metal one power post contacted gate pitch (CPP) of 1 CPP. To further reduce voltage droop, a standard cell uses dual height and half the width of a single height cell along with placing power posts with 1 CPP. The placement of the multiple power rails of the dual height cell allows alignment of the power rails with power rails of other standard cells.

The present technology relates to an imaging element and a semiconductor chip that enable the imaging element to be shorter. A first chip including a photodiode, and a second chip including a circuit configured to process a signal from the photodiode are laminated, and an impurity layer is provided on a second surface opposite to a first surface of the second chip on which the first chip is laminated. The impurity layer is formed to have an impurity concentration higher than an impurity concentration of a semiconductor substrate constituting the second chip. In the present technology, for example, an imaging element that is configured by laminating a plurality of chips and is shorter and smaller can be applied.

Integrated circuit devices including standard cells are provided. The standard cells may include a first vertical field effect transistor (VFET) including a first channel region and having a first conductivity type and a second VFET including a second channel region and having a second conductivity type that is different from the first conductivity type. Each of the first channel region and the second channel region may extend longitudinally in a first horizontal direction, and the first channel region may be spaced apart from the second channel region in a second horizontal direction that is perpendicular to the first horizontal direction.

A vertical field effect transistor (VFET) cell implementing a VFET circuit over a plurality of gate grids includes: a 1.sup.st circuit including at least one VFET and provided over at least one gate grid; and a 2.sup.nd circuit including at least one VFET and provided over at least one gate grid formed on a left or right side of the 1.sup.st circuit, wherein a gate of the VFET of the 1.sup.st circuit is configured to share a gate signal or a source/drain signal of the VFET of the 2.sup.nd circuit, and the 1.sup.st circuit is an (X−1)-contacted poly pitch (CPP) circuit, which is (X−1) CPP wide, converted from an X-CPP circuit which is X CPP wide and performs a same logic function as the (X−1)-CPP circuit, X being an integer greater than 1.

An integrated circuit including a first active region and a second active region extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; a power rail and a ground rail extending in the first direction and spaced apart from the first and second active regions and each other in the second direction; source/drain contacts extending in the second direction on at least a portion of the first or second active region, gate structures extending in the second direction and on at least a portion of the first and second active regions, a power rail configured to supply power through source/drain contact vias, and a ground rail configured to supply a ground voltage through source/drain contact vias.

A voltage level shifter cell, which is configured to convert voltage levels of input signals of multi-bits, includes: a first circuit area including a first voltage level shifter configured to convert a 1-bit first input signal from among the input signals; and a second circuit area including a second voltage level shifter configured to convert a 1-bit second input signal from among the input signals, wherein the first circuit area and the second circuit area share a first N-well to which a first power voltage is applied, and the first circuit area and the second circuit area share a second N-well to which a second power voltage is applied, wherein the first N-well is formed to extend in a first direction, and the first N-well and the second N-well are arranged to overlap in a second direction crossing the first direction.

The semiconductor structure includes a semiconductor substrate having active regions; field-effect devices disposed on the semiconductor substrate, the field-effect devices including gate stacks with elongated shape oriented in a first direction; a first metal layer disposed over the gate stacks, the first metal layer including first metal lines oriented in a second direction being orthogonal to the first direction; a second metal layer disposed over the first metal layer, the second metal layer including second metal lines oriented in the first direction; and a third metal layer disposed over the second metal layer, the third metal layer including third metal lines oriented in the second direction. The first, second, and third metal lines have a first thickness T.sub.1, a second thickness T.sub.2, and t a third thickness T.sub.3, respectively. The second thickness is greater than the first thickness and the third thickness.

A semiconductor integrated circuit device includes a flipflop circuit using vertical nanowire (VNW) FETs. A latch unit of the flipflop circuit includes: a feedback node; first p-type and n-type transistors each of which receives an input signal at one node and is connected to the feedback node at the other node; and second p-type and n-type transistors each connected to the feedback node at one node. In a standard cell, the tops of the first and second p-type and n-type transistors are connected to the feedback node.

The semiconductor structure includes a semiconductor substrate having active regions; field-effect devices disposed on the semiconductor substrate, the field-effect devices including gate stacks with elongated shape oriented in a first direction; a first metal layer disposed over the gate stacks, the first metal layer including first metal lines oriented in a second direction being orthogonal to the first direction; a second metal layer disposed over the first metal layer, the second metal layer including second metal lines oriented in the first direction; and a third metal layer disposed over the second metal layer, the third metal layer including third metal lines oriented in the second direction. The first, second, and third metal lines have a first thickness T.sub.1, a second thickness T.sub.2, and t a third thickness T.sub.3, respectively. The second thickness is greater than the first thickness and the third thickness.