A method includes: in a semiconductor wafer having a first semiconductor layer and a second semiconductor layer adjoining the first semiconductor layer, forming a porous region extending from a front surface into the first semiconductor layer; and removing the porous region by an etching process, wherein a doping concentration of the second semiconductor layer is less than 10.sup.−2 times a doping concentration of the first semiconductor layer and/or a doping type of the second semiconductor layer is complementary to a doping type of the first semiconductor layer, wherein forming the porous region comprises bringing in contact a porosifying agent with the front surface of the first semiconductor layer and applying a voltage between the first semiconductor layer and a first electrode that is in contact with the porosifying agent, wherein applying the voltage comprises applying the voltage between the first electrode and an edge region of the first semiconductor layer.

A wafer having a semiconductor substrate including a peripheral region and a central region, an insulating layer and a semiconductor layer is prepared first. Next, a plurality of trenches penetrating through the semiconductor layer and the insulating layer and reaching an inside of the semiconductor substrate are formed. Next, an inside of each of the plurality of trenches is filled with an insulating film, so that a plurality of element isolating portions is formed. Next, in the central region, the semiconductor layer exposed from a resist pattern is removed. The end portion closest to the outer edge of the semiconductor substrate among ends of the resist pattern used for removing the semiconductor layer in the central region is formed so as to be positioned closer to the outer edge of the semiconductor substrate than a position of the end portion closest to the outer edge of the semiconductor substrate among ends of the resist pattern used for forming the trenches.

A method includes: in a semiconductor wafer including a first semiconductor layer and a second semiconductor layer adjoining the first semiconductor layer, forming a porous region extending from a first surface into the first semiconductor layer; and removing the porous region by an etching process, wherein a doping concentration of the second semiconductor layer is less than 10.sup.−2 times a doping concentration of the first semiconductor layer and/or a doping type of the second semiconductor layer is complementary to a doping type of the first semiconductor layer.

Direct growth methods for preparing diamond-assisted heat-dissipation silicon carbide substrates of GaN-HEMTs are disclosed. In an embodiment, the direct growth method includes the following steps: (1) etching holes in a surface of a silicon carbide substrate to produce a silicon carbide wafer; (2) ultrasonic cleaning the produced silicon carbide wafer; (3) establishing an auxiliary nucleation point on a surface of the silicon carbide wafer; (4) depositing a diamond layer; (5) removing the portion of the diamond layer on the upper surface while retaining the portion of the diamond layer in the holes; (6) ultrasonic cleaning; and (7) depositing diamond in the holes on the silicon carbide wafer until the holes are fully filled.

A substrate for epitaxial growth includes a first surface to be processed, and a second surface opposite to the first surface. When being viewed from above the first surface, the substrate is divided into a modified region and a non-modified region. The modified region is partitioned from the non-modified region by a border which is located at a predetermined position in the substrate, and has a plurality of modified points.

A substrate has a front side including an electrical circuit and a rear side including an exposed zone that faces the electrical circuit. In an electrochemical treatment step, an electrical potential is laterally applied at least to the exposed zone of the rear side of the substrate, while the exposed zone is in contact with a chemically reactive substance. The electrical potential causes a lateral flow of electrical current at least in the exposed zone of the substrate. The lateral flow of current and the chemically reactive substance alter the substrate in at least the exposed zone.

The invention provides a method for polishing or planarizing a wafer of at least one of semiconductor, optical and magnetic substrates. The method includes rotating a polishing pad, the rotating polishing pad having radial feeder grooves in the polishing layer separating the polishing layer into polishing regions. The polishing regions are circular sectors defined by two adjacent radial feeder grooves. The radial feeder grooves extend from a location adjacent the center to a location adjacent the outer edge. Each polishing region includes a series of biased grooves connecting a pair of adjacent radial feeder grooves. Pressing and rotating the wafer against the rotating polishing pad for multiple rotations of the polishing pad adjusts polishing by either increasing or decreasing residence time of the polishing fluid under the wafer.

The polishing pad is suitable for polishing or planarizing a wafer of at least one of semiconductor, optical and magnetic substrates. The polishing pad includes radial feeder grooves in a polishing layer separating the polishing layer into polishing regions. The radial feeder grooves extend at least from a location adjacent the center to a location adjacent the outer edge of the polishing pad. Each polishing region including a series of biased grooves that connects a pair of adjacent radial feeder grooves. A majority of the biased grooves having either an inward bias toward the center of the polishing pad or an outward bias for directing polishing fluid toward the outer edge of the polishing pad.

One or more semiconductor manufacturing methods and/or semiconductor arrangements are provided. In an embodiment, a silicon carbide (SiC) layer is provided. The SiC layer has a first portion overlying a second portion. The first portion has a first side distal the second portion and a second side proximal the second portion. The first portion is converted into a porous layer overlying the second portion. The porous layer has a first side distal the second portion and a second side proximal the second portion. The porous layer is removed to expose a first side of the second portion. After removing the porous layer, the first side of the second portion has a surface roughness less than a surface roughness of the first side of the first portion and/or less than a surface roughness of the first side of the porous layer.

An integrated circuit (IC) may include an active device layer on a front-side surface of a semiconductor device substrate. The IC may also include a front-side dielectric layer having a first surface opposite a second surface, the first surface contacting the active device layer. The IC may further include a porous semiconductor handle substrate contacting the second surface of the front-side dielectric layer. The porous semiconductor handle substrate may be uniformly doped.