This disclosure relates to a composition that includes at least one first ruthenium removal rate enhancer; at least one copper removal rate inhibitor; at least one low-k removal rate inhibitor; and an aqueous solvent.

The present invention provides a means capable of sufficiently removing a residue containing inorganic oxide abrasive grains present on the surface of a polished object to be polished containing silicon nitride. One aspect of the present invention relates to a surface treatment method for reducing a residue containing inorganic oxide abrasive grains on a surface of a polished object to be polished containing silicon nitride using a composition for surface treatment, wherein the composition for surface treatment contains a zeta potential adjusting agent having a negatively charged functional group and having a viscosity of an aqueous solution having a concentration of 20% by mass at 25° C. of 10 mPa.Math.s or more and a dispersing medium, and the surface treatment method includes controlling a zeta potential of the silicon nitride and a zeta potential of the inorganic oxide abrasive grains each to −30 mV or less using the composition for surface treatment.

The present invention provides a unit that can sufficiently remove a residue containing inorganic oxide abrasive grains present on the surface of a polished object to be polished containing silicon oxide. One aspect of the present invention relates to a surface treatment method for reducing a residue containing inorganic oxide abrasive grains on a surface of a polished object to be polished containing silicon oxide using a composition for surface treatment, wherein the composition for surface treatment contains a zeta potential adjusting agent having an sp value of more than 9 and 11 or less and having a negatively charged functional group and a dispersing medium, and the surface treatment method includes negatively controlling a zeta potential of the silicon oxide and controlling a zeta potential of the inorganic oxide abrasive grains to −30 mV or less using the surface treatment composition.

The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The manufacturing method of a semiconductor structure includes: providing a substrate, where a plurality of contact pads are formed on the substrate; depositing a dielectric layer on the substrate, where the dielectric layer fills gaps between the contact pads and covers the contact pads; and etching the dielectric layer through a plasma etching process to expose the contact pads, where an etching gas used in the plasma etching process includes an oxygen-free etching gas. The manufacturing method can avoid the formation of metal oxides on the contact pads, and avoid residual conductive metal particles or metal compounds on surfaces of the contact pads and the adjacent dielectric layers, which is beneficial to ensure the electrical performance of the semiconductor structure, thereby improving the use reliability of the semiconductor structure.

The present application provides a semiconductor structure and a forming method thereof. The method of forming the semiconductor structure includes: forming a capacitor base, the capacitor base including a plurality of capacitor switching structures and an isolation layer located between adjacent capacitor switching structures and covering top surfaces of the capacitor switching structures; removing the isolation layer covering the top surfaces of the capacitor switching structures, and exposing the capacitor switching structures; oxidizing a surface of the capacitor base exposing the capacitor switching structures, and forming an oxide layer; and removing the oxide layer, and exposing the capacitor switching structures.

Provided are formulations that offer a high cleaning effect on inorganic particles, organic residues, chemical residues, reaction products on the surface due to interaction of the wafer surface with the Chemical Mechanical Planarization (CMP) slurry and elevated levels of undesirable metals on the surface left on the semiconductor devices after the CMP. The post-CMP cleaning formulations comprise one or more organic acid, one or more polymer and a fluoride compound with pH<7 and optionally a surfactant with two sulfonic acid groups.

The present disclosure provides a roller for cleaning a backside of a wafer. The backside of the wafer has a central region and a periphery region surrounding the central region. The roller includes an upper element, a bottom element, and an axis element for connecting the upper element and the bottom element. The upper element of the roller is configured to contact with a frontside of the wafer. The bottom element is configured to contact with the backside of the wafer and remove particles from the periphery region of the backside of the wafer. The bottom element is made of materials selected from a group comprising abrasive pads, sand papers, and asbestos.

An intermediate raw material according to the present invention includes a charge control agent having a critical packing parameter of 0.6 or more and a dispersing medium and a pH of the intermediate raw material is less than 7.

A cleaning system includes at least one cleaning module configured to receive a substrate after a chemical mechanical polishing (CMP) process and to remove contaminants on the substrate using a cleaning solution. The cleaning system further includes a cleaning solution supply system configured to supply the cleaning solution to the at least one cleaning module. The cleaning solution supply system includes at least one temperature control system. The at least one temperature control system includes a heating device configured to heat the cleaning solution, a cooling device configured to cool the cleaning solution, a temperature sensor configured to monitor a temperature of the cleaning solution, and a temperature controller configured to control the heating device and the cooling device.

A method for manufacturing a semiconductor device is provided. The method includes a step of performing a chemical mechanical polishing process on a first silicon oxide layer to form a planar surface layer; surface treatment is performed on the planar surface layer to form a treated planarization layer, and a second silicon oxide layer is formed on the treated planarization layer.