This disclosure relates to a composition that includes at least one first ruthenium removal rate enhancer; at least one copper removal rate inhibitor; at least one low-k removal rate inhibitor; and an aqueous solvent.

A method for processing a semiconductor structure and a method for forming a word line structure are provided. The method for processing the semiconductor structure includes: providing a semiconductor structure including a groove and a metal layer located in the groove, where an edge position of a top surface of the metal layer is higher than a center position of the top surface of the metal layer; enabling the semiconductor structure to be in a rotating state; and performing at least one metal surface planarization process on the semiconductor structure, so that the top surface of the metal layer after being processed is more planar than the top surface of the metal layer before being processed. Each of the at least one metal surface planarization process includes: etching the top surface of the metal layer by a first reagent; and cleaning the semiconductor structure by a second reagent.

Provided are formulations that offer a high cleaning effect on inorganic particles, organic residues, chemical residues, reaction products on the surface due to interaction of the wafer surface with the Chemical Mechanical Planarization (CMP) slurry and elevated levels of undesirable metals on the surface left on the semiconductor devices after the CMP. The post-CMP cleaning formulations comprise one or more organic acid, one or more polymer and a fluoride compound with pH<7 and optionally a surfactant with two sulfonic acid groups.

A substrate cleaning system includes a cleaner module to clean a substrate after polishing of the substrate, a drier module to dry the substrate after cleaning by the cleaner module, a substrate support movable along a first axis from a first position in the drier module to a second position outside the drier module, and an in-line metrology station including a line-scan camera positioned to scan the substrate as the substrate is held by the substrate support and the substrate support is between the first position to the second position. The first axis is substantially parallel to a face of the substrate as held in by the substrate support.

An object of the present invention is to provide a treatment liquid for a semiconductor device, which is excellent in removal performance for residues present on a substrate, and to provide a substrate washing method using the treatment liquid.

The treatment liquid of the present invention is a treatment liquid for a semiconductor device, which includes water, a basic compound, hexylene glycol, and a compound A that is at least one kind selected from the group consisting of isobutene, (E)-2-methyl-1,3-pentadiene, 4-methyl-1,3-pentadiene, 2,2,4-trimethyloxetane, 4-methyl-3-penten-2-ol, and 2,4,4,6-tetramethyl-1,3-dioxane.

The present disclosure provides a roller for cleaning a backside of a wafer. The backside of the wafer has a central region and a periphery region surrounding the central region. The roller includes an upper element, a bottom element, and an axis element for connecting the upper element and the bottom element. The upper element of the roller is configured to contact with a frontside of the wafer. The bottom element is configured to contact with the backside of the wafer and remove particles from the periphery region of the backside of the wafer. The bottom element is made of materials selected from a group comprising abrasive pads, sand papers, and asbestos.

A method for fabricating a planarized planarization layer for an integrated circuit device is described. A barrier layer is deposited over a planarization layer. Next, a liner layer is deposited on the barrier layer. An overburden layer is deposited on the liner layer. A first chemical mechanical polishing (CMP) process is performed on the overburden layer. A surface conversion process is performed on uncovered portions of a top surface of the planarization layer which are not protected by the polished overburden layer. A first wet etch is performed of the planarization layer. In embodiments, the first wet etch is selective to metal overburden layer as compared to the planarization layer. A second wet etch is performed removing the liner layer, the diffusion barrier layer and the metal overburden layer. In embodiments, the second wet etch is selective to the planarization layer as compared to the overburden layer.

In an embodiment, a device includes: a processor die including circuit blocks, the circuit blocks including active devices of a first technology node; a power gating die including power semiconductor devices of a second technology node, the second technology node larger than the first technology node; and a first redistribution structure including first metallization patterns, the first metallization patterns including power supply source lines and power supply ground lines, where a first subset of the circuit blocks is electrically coupled to the power supply source lines and the power supply ground lines through the power semiconductor devices, and a second subset of the circuit blocks is permanently electrically coupled to the power supply source lines and the power supply ground lines.

In an embodiment, a device includes: a processor die including circuit blocks, the circuit blocks including active devices of a first technology node; a power gating die including power semiconductor devices of a second technology node, the second technology node larger than the first technology node; and a first redistribution structure including first metallization patterns, the first metallization patterns including power supply source lines and power supply ground lines, where a first subset of the circuit blocks is electrically coupled to the power supply source lines and the power supply ground lines through the power semiconductor devices, and a second subset of the circuit blocks is permanently electrically coupled to the power supply source lines and the power supply ground lines.

A treatment liquid is a treatment liquid including water; a cationic compound; an anionic compound selected from the group consisting of a resin having a carboxy group or a salt thereof, a resin having a sulfo group or a salt thereof, a resin having a phosphorous acid group or a salt thereof, and a resin having a phosphoric acid group or a salt thereof; and an oxidizing agent, in which the treatment liquid has a pH of 7.0 or less, and the treatment liquid is substantially free of abrasive grains.