A substrate processing method includes providing a substrate with a silicon-containing film in a chamber, supplying a process gas containing an HF gas, a phosphorus halide gas, and at least one gas selected from the group consisting of a C.sub.4H.sub.2F.sub.6 gas, a C.sub.4H.sub.2F.sub.8 gas, a C.sub.3H.sub.2F.sub.4 gas, and a C.sub.3H.sub.2F.sub.6 gas into the chamber to generate plasma, and etching the silicon-containing film in the substrate.

Provided are a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate, a semiconductor device structure, a doped dielectric layer and an interlayer dielectric layer. The substrate has a first surface and a second surface opposite to each other. The semiconductor device structure is disposed on the first surface. The doped dielectric layer is disposed on the second surface. The interlayer dielectric layer is disposed on the doped dielectric layer.

Some embodiments include a method of forming an integrated assembly. A first stack is formed over a conductive structure. The first stack includes a second layer between first and third layers. The first and third layers are conductive. A first opening is formed through the first stack. A sacrificial material is formed within the first opening. A second stack is formed over the first stack. The second stack has alternating first and second levels. A second opening is formed through the second stack and through the sacrificial material. First semiconductor material is formed within the second opening. A third opening is formed through the second stack, through the third layer, and to the second layer. The second layer is removed, forming a conduit. Second semiconductor material is formed within the conduit. Dopant is out-diffused from the second semiconductor material into the first semiconductor material. Some embodiments include integrated assemblies.

An air gap forming method of forming an air gap in a gap structure having an upper surface, a lower surface, and a sidewall connecting the upper and lower surface, includes: repeatedly performing a selective deposition cycle, wherein the selective deposition cycle includes supplying a deposition inhibitor onto a substrate including the gap structure; and selectively forming a material layer on the upper surface compared to the sidewall.

Methods and devices for forming a conductive line disposed over a substrate. A first dielectric layer is disposed over the substrate and coplanar with the conductive line. A second dielectric layer disposed over the conductive line and a third dielectric layer disposed over the first dielectric layer. A via extends through the second dielectric layer and is coupled to the conductive line. The second dielectric layer and the third dielectric layer are coplanar and the second and third dielectric layers have a different composition. In some embodiments, the second dielectric layer is selectively deposited on the conductive line.

A semiconductor device includes: at least one gate structure comprising a gate electrode over a substrate, the gate electrode comprising a conductive material; and a first dielectric layer disposed along one or more side wall of the at least one gate structure, the first dielectric layer comprising fluorine doped silicon oxycarbonitride or fluorine doped silicon oxycarbide.

An etching method of the invention includes: a resist pattern-forming step of forming a resist layer on a target object, the resist layer being formed of a resin, the resist layer having a resist pattern; an etching step of etching the target object via the resist layer having the resist pattern; and a resist protective film-forming step of forming a resist protective film on the resist layer. The etching step is repetitively carried out multiple times. After the etching steps are repetitively carried out multiple times, the resist protective film-forming step is carried out.

A semiconductor device includes: at least one gate structure comprising a gate electrode over a substrate, the gate electrode comprising a conductive material; and a first dielectric layer disposed along one or more side wall of the at least one gate structure, the first dielectric layer comprising fluorine doped silicon oxycarbonitride or fluorine doped silicon oxycarbide.

A method for activating an exposed layer of a structure including a provision of a structure including an exposed layer, a deposition of a layer based on a material of formula Si.sub.aY.sub.bX.sub.c, with X chosen from among fluorine F and chlorine Cl, and Y chosen from among oxygen O and nitrogen N, a, b and c being non-zero positive integers, a treatment of the layer Si.sub.aY.sub.bX.sub.c by an activation plasma based on at least one from among oxygen and nitrogen, the parameters of the deposition of the layer Si.sub.aY.sub.bX.sub.c being chosen so as to obtain a sufficiently low material density such that the layer Si.sub.aY.sub.bX.sub.c is at least partially consumed by the activation plasma.

A method of making a monolithic three dimensional NAND string comprising forming a stack of alternating layers of a first material and a second material different from the first material over a substrate, forming an at least one front side opening in the stack and forming at least a portion of a memory film in the at least one front side opening. The method also includes forming a semiconductor channel in the at least one front side opening and doping at least one of the memory film and the semiconductor channel with fluorine in-situ during deposition or by annealing in a fluorine containing atmosphere.