Method for fabricating transistors for an integrated 3D circuit, comprising: a) forming, on a given level of transistors made in a first semiconductor layer: a stack comprising a first region of a second semiconductor zone suitable for an N-type transistor channel and a second region of the second semiconductor zone suitable for a P-type transistor channel of a higher level, the stack moreover comprising a ground plane continuous layer (40), as well as an insulating layer between the ground plane and the second semiconductor layer, then b) exposing source and drain zones of the circuit to a laser (L), so as to carry out at least one thermal activation annealing, where the exposed source and drain zones are located next to an upper surface of the ground plane continuous layer, where the ground plane continuous layer is configured so as to protect at least a part of the circuit located on the side of a lower face of the ground plane continuous layer from the laser, then c) carrying out cutting up of the ground plane continuous layer (40) into at least one first portion and one second portion separated from the first portion, where the first portion is configured to allow biasing of the first region, where the second portion is configured to allow biasing of the second region.

A modified trench metal-semiconductor alloy formation method involves depositing a layer of a printable dielectric or a sacrificial carbon material within a trench structure and over contact regions of a semiconductor device, and then selectively removing the printable dielectric or sacrificial carbon material to segment the trench and form plural contact vias. A metallization layer is formed within the contact vias and over the contact regions.

A semiconductor device is provided comprising a substrate, two or more semiconductor fins, and one or more gates. A flowable oxide layer is deposited on the semiconductor device. An area between the two or more semiconductor fins is etched such that the substrate is exposed. An insulating layer is deposited within the etched area. At least the flowable oxide layer is removed.

Method for fabricating transistors for an integrated 3D circuit, comprising: a) forming, on a given level of transistors made in a first semiconductor layer: a stack comprising a first region of a second semiconductor zone suitable for an N-type transistor channel and a second region of the second semiconductor zone suitable for a P-type transistor channel of a higher level, the stack moreover comprising a ground plane continuous layer (40), as well as an insulating layer between the ground plane and the second semiconductor layer, then b) exposing source and drain zones of the circuit to a laser (L), so as to carry out at least one thermal activation annealing, where the exposed source and drain zones are located next to an upper surface of the ground plane continuous layer, where the ground plane continuous layer is configured so as to protect at least a part of the circuit located on the side of a lower face of the ground plane continuous layer from the laser, then c) carrying out cutting up of the ground plane continuous layer (40) into at least one first portion and one second portion separated from the first portion, where the first portion is configured to allow biasing of the first region, where the second portion is configured to allow biasing of the second region.

A semiconductor structure includes a semiconductor substrate having an outer surface; a plurality of oxide regions, located outward of the outer surface, and defining a plurality of metal-gate-stack-receiving cavities; and a liner interspersed between the plurality of oxide regions and the semiconductor substrate and between the plurality of oxide regions and the plurality of metal-gate-stack-receiving cavities. A layer of high-K material is deposited over the semiconductor structure, including on outer surfaces of the plurality of oxide regions, outer edges of the liner, on walls of the plurality of metal-gate-stack-receiving cavities, and on the outer surface of the semiconductor substrate within the plurality of metal-gate-stack-receiving cavities. The layer of high-K material is chamfered to remove same from the outer surfaces of the plurality of oxide regions, the outer edges of the liner, and partially down the walls of the plurality of metal-gate-stack-receiving cavities.

In one aspect, a method of forming a wiring layer on a wafer is provided which includes: depositing a HSQ layer onto the wafer; cross-linking a first portion(s) of the HSQ layer using e-beam lithography; depositing a hardmask material onto the HSQ layer; patterning the hardmask using optical lithography, wherein the patterned hardmask covers a second portion(s) of the HSQ layer; patterning the HSQ layer using the patterned hardmask in a manner such that i) the first portion(s) of the HSQ layer remain and ii) the second portion(s) of the HSQ layer covered by the patterned hardmask remain, wherein by way of the patterning step trenches are formed in the HSQ layer; and filling the trenches with a conductive material to form the wiring layer on the wafer.

A semiconductor device is provided comprising a substrate, two or more semiconductor fins, and one or more gates. A flowable oxide layer is deposited on the semiconductor device. An area between the two or more semiconductor fins is etched such that the substrate is exposed. An insulating layer is deposited within the etched area. At least the flowable oxide layer is removed.

A method for forming a nanogap includes forming a knockoff feature on a dielectric layer and forming a trench in the dielectric layer on opposite sides of the knockoff feature. A noble metal is deposited in the trenches and over the knockoff feature. A top surface is polished to level the noble metal in the trenches with a top of the dielectric layer to form electrodes in the trenches and to remove the noble metal from the knockoff feature. A nanochannel is etched into the dielectric layer such that the knockoff feature is positioned within the nanochannel. The knockoff feature is removed to form a nanogap between the electrodes.

A semiconductor structure includes a semiconductor substrate having an outer surface; a plurality of oxide regions, located outward of the outer surface, and defining a plurality of metal-gate-stack-receiving cavities; and a liner interspersed between the plurality of oxide regions and the semiconductor substrate and between the plurality of oxide regions and the plurality of metal-gate-stack-receiving cavities. A layer of high-K material is deposited over the semiconductor structure, including on outer surfaces of the plurality of oxide regions, outer edges of the liner, on walls of the plurality of metal-gate-stack-receiving cavities, and on the outer surface of the semiconductor substrate within the plurality of metal-gate-stack-receiving cavities. The layer of high-K material is chamfered to remove same from the outer surfaces of the plurality of oxide regions, the outer edges of the liner, and partially down the walls of the plurality of metal-gate-stack-receiving cavities.

A semiconductor device is provided comprising a substrate, two or more semiconductor fins, and one or more gates. A flowable oxide layer is deposited on the semiconductor device. An area between the two or more semiconductor fins is etched such that the substrate is exposed. An insulating layer is deposited within the etched area. At least the flowable oxide layer is removed.