A device includes a fin extending from a semiconductor substrate, a gate stack over and along a sidewall of the fin, an isolation region surrounding the gate stack, an epitaxial source/drain region in the fin and adjacent the gate stack, and a source/drain contact extending through the isolation region, including a first silicide region in the epitaxial source/drain region, the first silicide region including NiSi.sub.2, a second silicide region on the first silicide region, the second silicide region including TiSi.sub.x, and a conductive material on the second silicide region.

Methods of forming metal silicon oxide layers and metal silicon oxynitride layers are disclosed. Exemplary methods include providing a silicon precursor to the reaction chamber for a silicon precursor pulse period, providing a first metal precursor to the reaction chamber for a first metal precursor pulse period, and providing a first reactant to the reaction chamber for a first reactant pulse period, wherein the silicon precursor pulse period and the first metal precursor pulse period overlap.

Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-κ dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium aluminum nitride (TiAIN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), tantalum oxide (TaO), and titanium aluminum carbide (TiAIC).

An example embodiment of the present disclosure involves a method for semiconductor device fabrication. The method comprises providing a structure that includes a conductive component and an interlayer dielectric (ILD) that includes silicon and surrounds the conductive component, and forming, over the conductive component and the ILD, an etch stop layer (ESL) that includes metal oxide. The ESL includes a first portion in contact with the conductive component and a second portion in contact with the ILD. The method further comprises baking the ESL to transform the metal oxide located in the second portion of the ESL into metal silicon oxide, and selectively etching the ESL so as to remove the first portion of the ESL but not the second portion of the ESL.

Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-κ dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), tantalum oxide (TaO), and titanium aluminum carbide (TiAlC).

A film forming method includes: preparing a substrate having a surface on which a first film containing boron and a second film made of a material different from that of the first film are formed; supplying a raw material gas, which contains halogen and an element X other than halogen, to the surface of the substrate; and supplying a plasmarized reaction gas, which contains oxygen, to the surface of the substrate, wherein a third film as an oxide film of the element X is selectively formed on the second film with respect to the first film by alternately supplying the raw material gas and the plasmarized reaction gas.

A method for forming a gate structure includes forming a trench within an interlayer dielectric layer (ILD) that is disposed on a semiconductor substrate, the trench exposing a top surface of the semiconductor substrate, forming an interfacial layer at a bottom of the trench, forming a dielectric layer within the trench, forming a work function metal layer on the dielectric layer, forming an in-situ nitride layer on the work function metal layer in the trench, performing a first cobalt deposition process to form a cobalt layer within the trench, performing a second cobalt deposition process to increase a thickness of the cobalt layer within the trench, and performing an electrochemical plating (ECP) process to fill the trench with cobalt.

A device includes a fin extending from a semiconductor substrate, a gate stack over and along a sidewall of the fin, an isolation region surrounding the gate stack, an epitaxial source/drain region in the fin and adjacent the gate stack, and a source/drain contact extending through the isolation region, including a first silicide region in the epitaxial source/drain region, the first silicide region including NiSi.sub.2, a second silicide region on the first silicide region, the second silicide region including TiSi.sub.x, and a conductive material on the second silicide region.

A semiconductor device with different configurations of gate structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes first and second gate structures disposed on first and second nanostructured channel regions, respectively. The first gate structure includes a nWFM layer disposed on the first nanostructured channel region, a barrier layer disposed on the nWFM layer, a first pWFM layer disposed on the barrier layer, and a first gate fill layer disposed on the first pWFM layer. Sidewalls of the first gate fill layer are in physical contact with the barrier layer. The second gate structure includes a gate dielectric layer disposed on the second nanostructured channel region, a second pWFM layer disposed on the gate dielectric layer, and a second gate fill layer disposed on the pWFM layer. Sidewalls of the second gate fill layer are in physical contact with the gate dielectric layer.

Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-κ dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), tantalum oxide (TaO), and titanium aluminum carbide (TiAlC).