There is provided a technique that includes selectively doping a metal film with a dopant by performing: supplying a dopant-containing gas containing the dopant to a substrate in which the metal film and a film other than the metal film are formed on a film in which the dopant is doped; and removing the dopant-containing gas from above the substrate.

Methods for depositing oxide thin films, such as metal oxide, metal silicates, silicon oxycarbide (SiOC) and silicon oxycarbonitride (SiOCN) thin films, on a substrate in a reaction space are provided. The methods can include at least one plasma enhanced atomic layer deposition (PEALD) cycle including alternately and sequentially contacting the substrate with a first reactant that comprises oxygen and a component of the oxide, and a second reactant comprising reactive species that does not include oxygen species. In some embodiments the plasma power used to generate the reactive species can be selected from a range to achieve a desired step coverage or wet etch rate ratio (WERR) for films deposited on three dimensional features. In some embodiments oxide thin films are selectively deposited on a first surface of a substrate relative to a second surface, such as on a dielectric surface relative to a metal or metallic surface.

A method for forming a gate structure includes forming a trench within an interlayer dielectric layer (ILD) that is disposed on a semiconductor substrate, the trench exposing a top surface of the semiconductor substrate, forming an interfacial layer at a bottom of the trench, forming a dielectric layer within the trench, forming a work function metal layer on the dielectric layer, forming an in-situ nitride layer on the work function metal layer in the trench, performing a first cobalt deposition process to form a cobalt layer within the trench, performing a second cobalt deposition process to increase a thickness of the cobalt layer within the trench, and performing an electrochemical plating (ECP) process to fill the trench with cobalt.

An example embodiment of the present disclosure involves a method for semiconductor device fabrication. The method comprises providing a structure that includes a conductive component and an interlayer dielectric (ILD) that includes silicon and surrounds the conductive component, and forming, over the conductive component and the ILD, an etch stop layer (ESL) that includes metal oxide. The ESL includes a first portion in contact with the conductive component and a second portion in contact with the ILD. The method further comprises baking the ESL to transform the metal oxide located in the second portion of the ESL into metal silicon oxide, and selectively etching the ESL so as to remove the first portion of the ESL but not the second portion of the ESL.

Gate fabrication techniques are disclosed herein for providing gate stacks and/or gate structures (e.g., high-k/metal gates) with improved profiles (e.g., minimal to no warping, bending, bowing, and necking and/or substantially vertical sidewalls), which may be implemented in various device types. For example, gate fabrication techniques disclosed herein provide gate stacks with stress-treated glue layers having a residual stress that is less than about 1.0 gigapascals (GPa) (e.g., about -2.5 GPa to about 0.8 GPa). In some embodiments, a stress-treated glue layer is provided by depositing a glue layer over a work function layer and performing a stress reduction treatment, such as an ion implantation process and/or an annealing process in a gas ambient, on the glue layer. In some embodiments, a stress-treated glue layer is provided by forming at least one glue sublayer/metal layer pair over a work function layer, performing a poisoning process, and forming a glue sublayer over the pair.

In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.

Semiconductor devices and methods of forming semiconductor devices are described. A method of forming metal silicon nitride films is disclosed. Some embodiments of the disclosure provide a process using ammonia plasma for treating a metal silicide or metal film to form a metal silicon nitride film. The ammonia plasma treatment generates NH* radicals that diffuse through the metal silicide to form a metal silicon nitride film that is substantially free of silicon nitride (SiN). The metal silicon nitride films have improved resistance relative to films deposited by thermal processes or plasma processes with a nitrogen plasma exposure.

A semiconductor device with different configurations of gate structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes first and second gate structures disposed on first and second nanostructured channel regions, respectively. The first gate structure includes a nWFM layer disposed on the first nanostructured channel region, a barrier layer disposed on the nWFM layer, a first pWFM layer disposed on the barrier layer, and a first gate fill layer disposed on the first pWFM layer. Sidewalls of the first gate fill layer are in physical contact with the barrier layer. The second gate structure includes a gate dielectric layer disposed on the second nanostructured channel region, a second pWFM layer disposed on the gate dielectric layer, and a second gate fill layer disposed on the pWFM layer. Sidewalls of the second gate fill layer are in physical contact with the gate dielectric layer.

There is provided a film formation method. The method comprises: preparing a substrate having a first region on which an oxide formed by oxidization of a surface of a conductive material is exposed and a second region on which an insulating material is exposed; replacing a film of the oxide with a film of boron oxide by supplying a boron halide gas to the substrate; etching the boron oxide film in the first region and forming a self-assembled monolayer film in the second region by supplying a gas of a fluorine-containing silane compound to the substrate; and forming a conductive target film selectively in the first region, from the first region and the second region, using the self-assembled monolayer film formed in the second region, the first region having the conductive material exposed thereon.

Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-K dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium aluminum nitride (TiAIN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), tantalum oxide (TaO), and titanium aluminum carbide (TiAIC).