Photovoltaics configured to be manufactured without epitaxial processes and methods for such manufacture are provided. Methods utilize bulk semiconducting crystal substrates, such as, for example, GaAs and InP such that epitaxy processes are not required. Nanowire etch and exfoliation processes are used allowing the manufacture of large numbers of photovoltaic cells per substrate wafer (e.g., greater than 100). Photovoltaic cells incorporate electron and hole selective contacts such that epitaxial heterojunctions are avoided during manufacture.

Provided is an apparatus for processing a substrate using plasma, in which an etching rate can be controlled using an insulation plate provided with an air-gap. The substrate processing apparatus includes a chamber including a processing space for processing a substrate using plasma, and a support module located in the processing space and for supporting the substrate, wherein the support module includes a support plate for receiving high frequency power and a first surface disposed under the support plate and facing the support plate, and at least one first recess is formed on the first surface.

A method for removing amorphous regions from a surface of a crystal substrate uses an accelerated neutral beam including reactive gas species for removing or reactively modifying material surfaces without sputtering. Accelerated neutral atom beam enabled surface reactions remove surface contaminants from substrate surfaces to create an interface region with exposed crystal lattice in preparation for next phase processing.

A method includes forming a first gate structure over a substrate, where the first gate structure is surrounded by a first dielectric layer; and forming a mask structure over the first gate structure and over the first dielectric layer, where forming the mask structure includes selectively forming a first capping layer over an upper surface of the first gate structure; and forming a second dielectric layer around the first capping layer. The method further includes forming a patterned dielectric layer over the mask structure, the patterned dielectric layer exposing a portion of the mask structure; removing the exposed portion of the mask structure and a portion of the first dielectric layer underlying the exposed portion of the mask structure, thereby forming a recess exposing a source/drain region adjacent to the first gate structure; and filling the recess with a conductive material.

A sintered body includes a crystal grain containing silicon nitride, and a grain boundary phase. If dielectric losses of the sintered body are measured while applying an alternating voltage to the sintered body and continuously changing a frequency of the alternating voltage from 50 Hz to 1 MHz, an average value ε.sub.A of dielectric losses of the sintered body in a frequency band from 800 kHz to 1 MHz and an average value ε.sub.B of dielectric losses of the sintered body in a frequency band from 100 Hz to 200 Hz satisfy an expression |ε.sub.A−ε.sub.B|≤0.1.

Method of doping a semiconductor sample in a uniform and carbon-free way, wherein said sample has a surface, comprising the following steps: A. removing oxides from at least part of the said surface; B. dip coating said at least part of the surface of the sample in a dopant based carbon-free solution of at least one dopant based carbon free substance diluted in water, wherein said at least one dopant based carbon free substance has a molecule comprising at least one dopant atom, wherein the dip coating is achieved by heating said dopant based carbon-free solution at a dip coating temperature from 65% to 100% of the boiling temperature of said dopant based carbon-free solution, thereby a self-assembled mono-layer including dopant atoms is formed; C. annealing said sample, wherein the annealing is configured to cause said dopant atoms included in said self-assembled mono-layer to be diffused into the sample.

A method for forming a contact surface on a top of a mesa structure formed on a semiconductor substrate deposited with an insulating layer. The method includes depositing a first resist layer over the insulating layer, depositing a second resist layer over the first resist layer, defining a first portion of the second resist layer, wherein the first portion overlaps the top of the mesa structure, forming a first opening in the first portion by treating the second resist layer to expose a second portion of the first resist layer beneath thereof, forming a second opening in the first resist layer, by treating the exposed second portion to expose a third portion of the insulating layer beneath thereof, and etching the exposed third portion to form the contact surface on the top of the mesa structure.

A method includes forming a first gate structure over a substrate, where the first gate structure is surrounded by a first dielectric layer; and forming a mask structure over the first gate structure and over the first dielectric layer, where forming the mask structure includes selectively forming a first capping layer over an upper surface of the first gate structure; and forming a second dielectric layer around the first capping layer. The method further includes forming a patterned dielectric layer over the mask structure, the patterned dielectric layer exposing a portion of the mask structure; removing the exposed portion of the mask structure and a portion of the first dielectric layer underlying the exposed portion of the mask structure, thereby forming a recess exposing a source/drain region adjacent to the first gate structure; and filling the recess with a conductive material.

A method for removing amorphous regions from a surface of a crystal substrate uses an accelerated neutral beam including reactive gas species for removing or reactively modifying material surfaces without sputtering. Accelerated neutral atom beam enabled surface reactions remove surface contaminants from substrate surfaces to create an interface region with exposed crystal lattice in preparation for next phase processing.

Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.