A sintered body includes a crystal grain containing silicon nitride, and a grain boundary phase. If dielectric losses of the sintered body are measured while applying an alternating voltage to the sintered body and continuously changing a frequency of the alternating voltage from 50 Hz to 1 MHz, an average value ε.sub.A of dielectric losses of the sintered body in a frequency band from 800 kHz to 1 MHz and an average value ε.sub.B of dielectric losses of the sintered body in a frequency band from 100 Hz to 200 Hz satisfy an expression |ε.sub.A−ε.sub.B|≤0.1.

A semiconductor device and method for manufacturing the semiconductor device are disclosed. Specifically, the semiconductor device may include a charge trapping layer with improved retention and speed for VNAND applications. The charge trapping layer may comprise an aluminum nitride (AlN) or aluminum oxynitride (AlON) layer.

A method for filling a gap feature on a substrate surface is disclosed. The method may include: providing a substrate comprising a non-planar surface including one or more gap features; depositing a metal oxide film over a surface of the one or more gap features by a cyclical deposition process; contacting the metal oxide with an organic ligand vapor; and converting at least a portion of the metal oxide film to a porous material thereby filling the one or more gap features. Semiconductor structures including a metal-organic framework material formed by the methods of the disclosure are also disclosed.

A structure body includes a base material and a siloxane based molecular membrane formed on the base material by use of an organic compound represented by Formula (1) or Formula (2): ##STR00001##
wherein any one of R1 to R5 is an amino group, others of R1 to R5 are each independently hydrogen or an alkyl group, R7 to R9 are each independently any one of hydroxy group, alkoxy group, alkyl group, and phenyl group on condition that one or more of R7 to R9 are each independently a hydroxy group or an alkoxy group, and R6 is an alkyl group.

A sintered body includes a crystal grain containing silicon nitride, and a grain boundary phase. If dielectric losses of the sintered body are measured while applying an alternating voltage to the sintered body and continuously changing a frequency of the alternating voltage from 50 Hz to 1 MHz, an average value ε.sub.A of dielectric losses of the sintered body in a frequency band from 800 kHz to 1 MHz and an average value ε.sub.B of dielectric losses of the sintered body in a frequency band from 100 Hz to 200 Hz satisfy an expression |ε.sub.A−ε.sub.B|≤0.1.

A method for filling a gap feature on a substrate surface is disclosed. The method may include: providing a substrate comprising a non-planar surface including one or more gap features; depositing a metal oxide film over a surface of the one or more gap features by a cyclical deposition process; contacting the metal oxide with an organic ligand vapor; and converting at least a portion of the metal oxide film to a porous material thereby filling the one or more gap features. Semiconductor structures including a metal-organic framework material formed by the methods of the disclosure are also disclosed.

Unwanted erosion of dielectric materials around a backside contact trench can be avoided or minimized employing an aluminum oxide liner. An aluminum oxide liner can be formed inside an insulating material layer in a backside contact trench to prevent collateral etching of the insulating material at an upper portion of the backside contact trench during an anisotropic etch that forms an insulating spacer. Alternatively, an aluminum oxide layer can be employed as a backside blocking dielectric layer. An upper portion of the aluminum oxide layer can be converted into an aluminum compound layer including aluminum and a non-metallic element other than oxygen at an upper portion of the trench, and can be employed as a protective layer during formation of a backside contact structure.

The present disclosure provides a semiconductor structure in accordance with some embodiments. The semiconductor structure includes a semiconductor feature, a passivation layer that includes indium sulfide formed over a surface of the semiconductor feature. More particularly, the surface of the semiconductor feature comprises indium-based III-V compound semiconductor material.

A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a gallium arsenide substrate, a thiourea-based passivation layer in contact with at least a top surface of the gallium arsenide substrate, and a capping layer in contact with the thiourea-based passivation layer. The method includes passivating a gallium arsenide substrate utilizing thiourea to form a passivation layer in contact with at least a top surface of the gallium arsenide substrate. The method further includes forming a capping layer in contact with at least a top surface of the passivation layer, and annealing the capping layer and the passivation layer.

Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.