A method for manufacturing a shallow trench isolation structure includes: providing a substrate and forming multiple first trenches in the substrate, in which a cross-sectional width of each first trench increases downward along a vertical direction; forming a continuous first isolation layer on a top of the substrate and inner sides of the multiple first trenches by a deposition process, in which parts of the first isolation layer located in the first trenches form second trenches, and in which a cross-sectional width of each second trench remains constant downward along the vertical direction; and forming a continuous second isolation layer on a surface of the first isolation layer by an ISSG process, in which parts of the second isolation layer located in the second trenches completely fill up the second trenches.

Exemplary methods of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. The methods may include depositing a silicon-containing layer on surfaces defining the processing region of the semiconductor processing chamber. The methods may include forming a plasma of a hydrogen-containing precursor within the processing region of the semiconductor processing chamber. The methods may include depositing a silicon-containing material on a substrate disposed within the processing region of the semiconductor processing chamber.

The present technology includes improved gas distribution designs for forming uniform plasmas during semiconductor processing operations or for treating the interior of semiconductor processing chambers. While conventional gas distribution assemblies may receive a specific reactant or reactant ratio which is then distributed into the plasma region, the presently described technology allows for improved control of the reactant input distribution. The technology allows for separate flows of reactants to different regions of the plasma to offset any irregularities observed in process uniformity. A first precursor may be delivered to the center of the plasma above the center of the substrate/pedestal while a second precursor may be delivered to an outer portion of the plasma above an outer portion of the substrate/pedestal. In so doing, a substrate residing on the pedestal may experience a more uniform etch or deposition profile across the entire surface.

A film-forming apparatus for forming a predetermined film on a substrate by plasma ALD includes a chamber, a stage, a shower head having an upper electrode and a shower plate insulated from the upper electrode, a first high-frequency power supply connected to the upper electrode, and a second high-frequency power supply connected to an electrode contained in the stage. A high-frequency power is supplied from the first high-frequency power supply to the upper electrode, thereby forming a high-frequency electric field between the upper electrode and the shower plate and generating a first capacitively coupled plasma. A high-frequency power is supplied from the second high-frequency power supply to the electrode, thereby forming a high-frequency electric field between the shower plate and the electrode in the stage and generating a second capacitively coupled plasma that is independent from the first capacitively coupled plasma.

PECVD methods for depositing a film at a low deposition rate comprising intermittent activation of the plasma are disclosed. The flowable film can be deposited using at least a polysilane precursor and a plasma gas. The deposition rate of the disclosed processes may be less than 500 Å/min.

Localized stresses can be modulated in a film deposited on a bowed semiconductor substrate by selectively and locally curing the film by ultraviolet (UV) radiation. A bowed semiconductor substrate can be asymmetrically bowed. A UV-curable film is deposited on the front side or the backside of the bowed semiconductor substrate. A mask is provided between the UV-curable film and a UV source, where openings in the mask are patterned to selectively define exposed regions and non-exposed regions of the UV-curable film. Exposed regions of the UV-curable film modulate localized stresses to mitigate bowing in the bowed semiconductor substrate.

A method of forming a semiconductor device includes: forming a dummy gate structure over a fin structure that protrudes above a substrate, where the fin structure includes a fin and a layer stack over the fin, where the layer stack comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the fin structure on opposing sides of the dummy gate structure, where the openings exposes first portions of the first semiconductor material and second portions of the second semiconductor material; recessing the exposed first portions of the first semiconductor material to form sidewall recesses in the first semiconductor material; lining the sidewall recesses with a first dielectric material; depositing a second dielectric material in the sidewall recesses on the first dielectric material; after depositing the second dielectric material, annealing the second dielectric material; and after the annealing, forming source/drain regions in the openings.

Methods and systems for forming a structure including a silicon carbide layer and structures formed using the methods and systems are disclosed. Exemplary methods include providing a silicon carbide precursor to the reaction chamber, forming a plasma within the reaction chamber to form an initially flowable, viscous silicon carbide material on a surface of the substrate, wherein the initially viscous carbon material becomes the silicon carbide layer. Exemplary methods can include use of a silicon carbide precursor that includes a carbon-carbon triple bond and/or use of a relatively low plasma power density (e.g., less than 3 W/cm.sup.2).

An yttrium compound and a method of manufacturing an integrated circuit device, the compound being represented by General Formula (I):

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A semiconductor device includes a gate extraction portion extracted from a gate electrode and extending from an active region to an outer peripheral region so as to be disposed above an end portion of a field insulating film. The end portion of the gate field insulating film above which the gate extraction portion is disposed is inclined in such a manner that a thickness of the field insulating film increases in a direction from the active region toward the outer peripheral region.