Stress memorization techniques (SMTs) for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a capping layer over a fin structure; forming an amorphous region within the fin structure while the capping layer is disposed over the fin structure; and performing an annealing process to recrystallize the amorphous region. The capping layer enables the fin structure to retain stress effects induced by forming the amorphous region and/or performing the annealing process.

According to the invention there is provided a method of filling one or more gaps created during manufacturing of a feature on a substrate by providing a deposition method comprising; introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant; introducing a second reactant to the substrate with a second dose. The first reactant is introduced with a subsaturating first dose reaching only a top area of the surface of the one or more gaps and the second reactant is introduced with a saturating second dose reaching a bottom area of the surface of the one or more gaps. A third reactant may be provided to the substrate in the reaction chamber with a third dose, the third reactant reacting with at least one of the first and second reactant.

Provided is a manufacturing method for a semiconductor device including forming a first electrode layer on a front surface of a wafer, implanting, into an outer peripheral region of the front surface of the wafer, a heavy ion of an element in third and subsequent rows of a periodic table, forming an oxide film in the outer peripheral region into which the heavy ion has been implanted, and forming a second electrode layer on the first electrode layer by plating. A dose of the heavy ion may be 1E15 cm.sup.−2 or more. A depth of an implantation range of the heavy ion into the wafer may be 0.02 μm or more. The heavy ion may be an As ion, a P ion, or an Ar ion.

Provided are a layer structure including a carbon-based material, a method of manufacturing the layer structure, an electronic device including the layer structure, and an electronic apparatus including the electronic device. The layer structure may include a lower layer, an ion implantation layer in the lower layer, and a carbon-based material layer on the ion implantation layer, wherein the ion implantation layer includes carbon. The ion implantation layer may include a trench, and the carbon-based material layer may be provided in the trench. The carbon-based material layer may be formed to coat an inner surface of the trench. The carbon-based material layer may fill at least a portion of the trench. The ion implantation concentration of the ion implantation layer may be uniform as a whole. The ion implantation layer may have an ion implantation concentration gradient in a given direction.

According to the invention there is provided a method of filling one or more gaps created during manufacturing of a feature on a substrate by providing a deposition method comprising; introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant; introducing a second reactant to the substrate with a second dose. The first reactant is introduced with a sub saturating first dose reaching only a top area of the surface of the one or more gaps and the second reactant is introduced with a saturating second dose reaching a bottom area of the surface of the one or more gaps. A third reactant may be provided to the substrate in the reaction chamber with a third dose, the third reactant reacting with at least one of the first and second reactant.

Embodiments described herein relate to apparatus and methods for processing a substrate. In one embodiment, a cluster tool apparatus is provided having a transfer chamber and a pre-clean chamber, a self-assembled monolayer (SAM) deposition chamber, an atomic layer deposition (ALD) chamber, and a post-processing chamber disposed about the transfer chamber. A substrate may be processed by the cluster tool and transferred between the pre-clean chamber, the SAM deposition chamber, the ALD chamber, and the post-processing chamber. Transfer of the substrate between each of the chambers may be facilitated by the transfer chamber which houses a transfer robot.

Chip structures and fabrication methods for forming such chip structures. A first device structure has a structural feature comprised of a first dielectric material and a second device structure has a structural feature comprised of a second dielectric material. A semiconductor layer has a first section adjacent to the structural feature of the first device structure and a second section adjacent to the structural feature of the second device structure. The first section of the semiconductor layer has a popped relationship relative to the structural feature comprised of the first dielectric material. The second section of the semiconductor layer includes a portion that has a pinned relationship relative to a portion of the structural feature comprised of the second dielectric material.

According to the invention there is provided a method of filling one or more gaps created during manufacturing of a feature on a substrate by providing a deposition method comprising; introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant; introducing a second reactant to the substrate with a second dose. The first reactant is introduced with a subsaturating first dose reaching only a top area of the surface of the one or more gaps and the second reactant is introduced with a saturating second dose reaching a bottom area of the surface of the one or more gaps. A third reactant may be provided to the substrate in the reaction chamber with a third dose, the third reactant reacting with at least one of the first and second reactant.

The present disclosure provides a method for forming a semiconductor structure. The method includes providing a substrate including a plurality of fin structures on the substrate; coating a first solution on the substrate to form a first dielectric layer; and coating a second solution on the first dielectric layer to form a second dielectric layer to cover the fin structures. The first solution has a first viscosity. The second solution has a second viscosity. In some embodiments, the second viscosity is greater than the first viscosity.

A gallium nitride based semiconductor device is provided, where when a thickness of a transition layer is defined as the followings, the thickness of the transition layer is less than 1.5 nm: (i) a distance between a depth position at which an atomic composition of nitrogen element constituting the gallium nitride based semiconductor layer is ½ relative to that at a position on the GaN based semiconductor layer side sufficiently away from the transition layer, and a depth position at which an atomic composition of a metal element is ½ of a value of a maximum if an atomic composition of the metal element constituting an insulating layer has the maximum, or a depth position at which an atomic composition of the metal element is ½ relative to that at a position on the insulating layer side sufficiently away from the transition layer if not having the maximum.