A display apparatus may include a base substrate including a first portion and a second portion smaller than the first portion, a plurality of pixels disposed on the first portion, a protection substrate disposed below the base substrate, and a groove disposed in a portion of the protection substrate and overlapped with the second portion. The groove may include a first region extending in a first direction, and a second region and a third region, which are arranged along the first direction, wherein the first region is interposed between the second region and the third region. The first and second portions may be arranged in a second direction crossing the first direction, and a width of each of the second and third regions may be larger than a first width of the first region, when measured in the second direction.

In method of manufacturing a semiconductor device, an opening is formed over a first conductive layer in a dielectric layer, a second conductive layer is formed over the first conductive layer in the opening without forming the second conductive layer on at least an upper surface of the dielectric layer, a third conductive layer is formed over the second conductive layer in the opening without forming the third conductive layer on at least an upper surface of the dielectric layer, and an upper layer is formed over the third conductive layer in the opening.

A manufacturing method of an indium tin oxide (ITO) thin film based on a solution method is disclosed. The manufacturing method includes: a step of providing an array substrate; a step of obtaining a dispersion solution by mixing ITO grains, an organic small molecule phase transfer agent, and an N-chlorosuccinimide (NCs) solution; a step of obtaining uniformly assembled ITO grains by coating the dispersion solution onto a passivation layer and baking to remove the organic small molecule phase transfer agent; and a step of obtaining the ITO thin film by annealing at an inert atmosphere to refine the ITO grains.

A method of manufacturing a semiconductor device includes forming a first nitride semiconductor layer containing Ga on a substrate; forming a first layer on the first nitride semiconductor layer; forming a second layer on the first layer; forming an opening in which the first nitride semiconductor layer is exposed in the second layer and the first layer; forming a second nitride semiconductor layer of a first conductivity type on a surface, exposed in the opening, of the first nitride semiconductor layer; removing the second layer using an acidic solution; and after removing the second layer, forming an electrode on the second nitride semiconductor layer. A first etching rate of the first layer for the acidic solution is lower than a second etching rate of the second layer for the acidic solution.

Disclosed a transient voltage suppressor and a method for manufacturing the same. According to the transient voltage suppressor, an additional gate stack layer is introduced based on the prior transient voltage suppressor, and the diffusion isolation regions are reused as the conductive vias, so that, the gate stack layer, the first doped region, the conductive vias, and the second semiconductor layer constitute a MOS transistor being coupled in parallel to the Zener diode or the avalanche diode of the transient voltage suppressor. When the current of the I/O terminal is relatively large, the MOS transistor is turned on to share part of the current of the I/O terminal through the Zener diode or the avalanche diode, thereby protecting the Zener diode or the avalanche diode from being damaged due to excessive current. Thus, the robustness of the transient voltage suppressor is improved without increasing the manufacture cost.

Aspects of the present technology are directed toward Integrated Circuits (IC) including a plurality of trenches disposed in a substrate about a set of silicide regions. The trenches can extend down into the substrate below the set of silicide regions. The silicide regions can be formed by implanting metal ions into portions of a substrate exposed by a mask layer with narrow pitch openings. The trenches can be formed by selectively etching the substrate utilizing the set of silicide regions as a trench mask. An semiconductor material with various degree of crystallinity can be grown from the silicide regions, in openings that extend through subsequently formed layers down to the silicide regions.

A method for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. In some embodiments, a first in-situ process including a pre-treatment process of the work-function metal layer is performed. By way of example, the pre-treatment process removes an oxidized layer of the work-function metal layer to form a treated work-function metal layer. In some embodiments, after performing the first in-situ process, a second in-situ process including a deposition process of another metal layer over the treated work-function metal layer is performed.

The present disclosure provides a technique capable of controlling a shape of an SAM. Provided is a method of forming a target film on a substrate, wherein the method includes preparing a substrate including a layer of a first conductive material formed on a surface of a first region, and a layer of an insulating material formed on a surface of a second region; forming carbon nanotubes on a surface of the layer of the first conductive material; and supplying a raw material gas for a self-assembled film to form the self-assembled film in a region of the surface of the layer of the first conductive material in which the carbon nanotubes have not been formed.

Implementations described herein generally relate to a method for forming a metal layer and to a method for forming an oxide layer on the metal layer. In one implementation, the metal layer is formed on a seed layer, and the seed layer helps the metal in the metal layer nucleate with small grain size without affecting the conductivity of the metal layer. The metal layer may be formed using plasma enhanced chemical vapor deposition (PECVD) and nitrogen gas may be flowed into the processing chamber along with the precursor gases. In another implementation, a barrier layer is formed on the metal layer in order to prevent the metal layer from being oxidized during subsequent oxide layer deposition process. In another implementation, the metal layer is treated prior to the deposition of the oxide layer in order to prevent the metal layer from being oxidized.

A semiconductor device has a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is less than the first height.