A semiconductor device such as a chip-scale package is provided. Aspects of the present disclosure further relate to a method for manufacturing such a device. According to an aspect of the present disclosure, a semiconductor device is provided that includes a conformal coating arranged on its sidewalls and on the perimeter part of the semiconductor die of the semiconductor device. To prevent the conformal coating from covering unwanted areas, such as electrical terminals, a sacrificial layer is arranged prior to arranging the conformal coating. By removing the sacrificial layer, the conformal coating can be removed locally. The conformal coating covers the perimeter part of the semiconductor die by the semiconductor device, in which part a remainder of a sawing line or dicing street is provided.

A semiconductor structure includes a semiconductor substrate, a metal layer, an interlayer dielectric (ILD) layer. The metal layer is disposed over the semiconductor substrate. The ILD layer is over the semiconductor substrate and laterally surrounding the metal layer, in which the ILD layer has a first portion in contact with a first sidewall of the metal layer and a second portion in contact with a second sidewall of the metal layer opposite to the first sidewall of the metal layer, and a width of the first portion of the ILD layer decreases as a distance from the semiconductor substrate increases.

A III-nitride-based semiconductor device is provided. The III-nitride semiconductor device includes a silicon substrate having a surface with a periodic array of recesses formed therein. A discontinuous insulating layer is formed within each recess of the periodic array of recesses such that a portion of the silicon substrate surface between adjacent recesses is free from coverage of the discontinuous insulating layer. A first epitaxial III-nitride semiconductor layer is formed over the silicon substrate with the periodic array of recesses and discontinuous insulating layer formed thereon. A second III-nitride semiconductor layer is disposed over the first III-nitride semiconductor layer and has a bandgap greater than a bandgap of the first III-nitride semiconductor layer. At least one source and at least one drain are disposed over the second III-nitride semiconductor layer. A gate is also disposed over the second III-nitride semiconductor layer between the source and the drain.

Flexible electrical devices comprising electrode layers on softening polymers and methods of manufacturing such devices, including lift-off processes for forming electrodes on softening polymers, processes for forming devices with a patterned double softening polymer layer, and solder reflow processes for forming electrical contacts on softening polymers.

A method for manufacturing a solid state device with a self-forming nanogap includes patterning a first metallic layer (M1) to form a first electrode on a substrate; depositing a self-assembling monolayer, SAM, layer over and around the first electrode; forming a second metallic layer (M2) in contact with the SAM layer and the substrate; and touchlessly removing parts of the second metallic layer (M2) that is formed directly above the SAM layer, to form a second electrode, and a nanogap between the first electrode and the second electrode.

A method for manufacturing semiconductor elements by a metal lift-off process and a semiconductor element manufactured thereby, include steps of photoresist-coating, exposing, developing, metal-coating, and lift-off. A photoresist layer can be removed with a photoresist stripper. Meanwhile, the metal on the top of the photoresist layer can also be removed when the photoresist layer is removed. The circuit layout required for the semiconductor element can thus be completed without an etching process. In addition, by setting the process parameters, the contour of the photoresist layer can present a certain angle, so that the metal on the surface of the photoresist layer can be completely removed, which saves costs and improves competitiveness.

A substrate, a first layer disposed on the substrate, and a second layer disposed on the first layer are provided. An opening is etched through the second layer to the first layer. A first portion of the first layer is etched through the opening using a first etchant, to expose a surface of the substrate through the opening. A feature is deposited on the surface of the substrate through the opening. A second portion of the first layer is etched using a gaseous etchant, to release the substrate from the second layer.

An electrical device, comprising a softening polymer layer, an electrode layer on a surface of the softening polymer layer and a cover polymer layer on the surface of the softening polymer layer. An opening in the polymer cover layer is filled with a reflowed solder, one end of the reflowed solder, located inside the opening, contacts a contact pad site portion of the electrode layer, and another end of the reflowed solder contacts an electrical connector electrode of the device.

A method of etching an organic or hybrid inorganic/organic material. The method etches molecular layer deposition coatings. An etching cycle comprises a first half reaction exposing the coating to a precursor. A second half reaction exposes a second precursor, removing or etching a portion of the coating.

A method for preparing film patterns; firstly, a complementary film pattern (1) to a desired film pattern (201) is prepared on a substrate (3) with an erasable agent; secondly, a whole layer of film (2) is formed on the complementary film pattern (1); and thirdly, the desired film pattern (201) is obtained by removing the complementary film pattern (1). The preparation method can simplify the production process and reduce the production cost of the film patterns.