The invention solves the problem of depressed SOA of a bipolar junction transistor (BJT) when operated in an open base configuration by integrating in the same semiconductor chip a switchable short between the base and the emitter of the BJT. The switchable short switches between a high resistive value when the collector voltage of the BJT is lower than the base voltage. and a lower resistive value when the collector voltage is higher than the voltage base to effectively lower the BJT current gain (h.sub.FE). The switchable short in one implementation of the invention is in the form of a MOSFET with its gate connected to the BJT collector. The invention further teaches disposing in the integrated circuit chip a junction diode with a breakdown voltage lower than the BVCBO of the BJT. The addition of the junction diode provides a measure of maintaining the effectiveness of the MOSFET as switchable short at a reduced size.

Provided are methods for producing n-doped graphene films. The method comprises contacting a graphene layer with an alkali metal-doped polymer layer. Compositions comprising (i) a substrate, (ii) a doped polymer, and (iii) graphene are also provided. The methods of the invention produce n-doped graphene films that are resistant to degradation, have high electrical conductivity, and low sheet resistance without altering the optical transmission of graphene.

The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The method of manufacturing a semiconductor structure includes: providing a base; forming a plurality of first trenches arranged in parallel at intervals and extending along a first direction, and an initial active region between two adjacent ones of the first trenches, wherein the initial active region includes a first initial source-drain region close to a bottom of the first trench, a second initial source-drain region away from the bottom of the first trench, and an initial channel region located between the first initial source-drain region and the second initial source-drain region; forming a protective dielectric layer, wherein the protective dielectric layer covers a sidewall of the second initial source-drain region and a sidewall of the initial channel region; thinning the first initial source-drain region.

This application provides a process for making a circuit of a bipolar junction transistor (BJT). The switchable short in one implementation of the invention is formed in a semiconductor wafer. A collector region is formed in the semiconductor wafer and inside of the collector region, a first base region is formed. An emitter region is formed inside the base region to form the BJT. A drain region is also formed inside the base region adjacent to the emitter region. A gate is formed over a portion of the base region adjacent to the drain region and the emitter region. The gate is connected to the collection region.

This application provides a process for making a circuit of a bipolar junction transistor (BJT). The switchable short in one implementation of the invention is formed in a semiconductor wafer. A collector region is formed in the semiconductor wafer and inside of the collector region, a first base region is formed. An emitter region is formed inside the base region to form the BJT. A drain region is also formed inside the base region adjacent to the emitter region. A gate is formed over a portion of the base region adjacent to the drain region and the emitter region. The gate is connected to the collection region.

The invention solves the problem of depressed SOA of a bipolar junction transistor (BJT) when operated in an open base configuration by integrating in the same semiconductor chip a switchable short between the base and the emitter of the BJT. The switchable short switches between a high resistive value when the collector voltage of the BJT is lower than the base voltage. and a lower resistive value when the collector voltage is higher than the voltage base to effectively lower the BJT current gain (h.sub.FE). The switchable short in one implementation of the invention is in the form of a MOSFET with its gate connected to the BJT collector. The invention further teaches disposing in the integrated circuit chip a junction diode with a breakdown voltage lower than the BVCBO of the BJT. The addition of the junction diode provides a measure of maintaining the effectiveness of the MOSFET as switchable short at a reduced size.

Disclosed is a high-quality and high-functional graphene-based TFT, including: a gate electrode, a gate insulating layer disposed on the gate electrode; an active layer including a nitrogen-doped graphene layer, on which disposed in a partial region of the gate insulating layer; a first electrode disposed on a region of one side of the active layer; and a second electrode disposed on a region of the other side of the active layer. The present invention allows obtaining the TFT having excellent characteristics by directly growing graphene on a Ti layer, implementing damages with remote plasma, and doping with nitrogen gas to fabricate a graphene active layer.

Methods of providing an air- and/or moisture-barrier coating on at least a portion of a two-dimensional material are described. In particular, the methods provide an improved approach for providing a doped two-dimensional material, preferably graphene, on a substrate wherein at least a portion of the two-dimensional material is coated with an air- and/or moisture-barrier coating that comprises an inorganic oxide, fluoride or sulfide. Two-dimensional materials provided with an air- and/or moisture impermeable inorganic oxide, fluoride or sulfide coating and an electronic device comprising the same are also described.

Disclosed are compositions and methods of semiconductors including tungsten oxyselenide (TOS) as a p-type dopant. The TOS is formed by introducing a single layer of tungsten diselenide (WSe.sub.2) to a semiconductor and subject the tungsten diselenide to a room-temperature UV plus ozone process. This process forms a TOS monolayer, which can be used as a universal p-type dopant for a variety of different semiconductors. Suitable semiconductor materials include, for example, graphene, carbon nanotubes, tungsten diselenide, and dinaphthothienothiophene (DNTT).

A method for thermally processing a substrate having a surface region and a buried region with a pulsed light beam, the substrate presenting an initial temperature-depth profile and the surface region presenting an initial surface temperature, including steps of: illuminating the surface region with a preliminary pulse so that it generates an amount of heat and reaches a predetermined preliminary surface temperature; and illuminating the surface region with a subsequent pulse after a time interval so that it reaches a predetermined subsequent surface temperature. The time interval is determined such that the surface region reaches a predetermined intermediate surface temperature greater than the initial surface temperature, such that during the time interval, the amount of heat is diffused within the substrate down to a predetermined depth so that the substrate presents a predetermined intermediate temperature-depth profile.