A method of splitting off a semiconductor wafer from a semiconductor bottle includes: forming a separation region within the semiconductor boule, the separation region having at least one altered physical property which increases thermo-mechanical stress within the separation region relative to the remainder of the semiconductor boule; and applying an external force to the semiconductor boule such that at least one crack propagates along the separation region and a wafer splits from the semiconductor boule.

A semiconductor device of embodiments includes: an electrode containing titanium (Ti); a silicon carbide layer; a first region provided between the silicon carbide layer and the electrode, containing silicon (Si) and oxygen (O), and having a thickness equal to or more than 2 nm and equal to or less than 10 nm; and a second region provided between the first region and the electrode and containing titanium (Ti) and silicon (Si).

A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

A semiconductor device according to one or more embodiments is disclosed that may include a first substrate comprising a single-crystalline SiC substrate; a second substrate comprising a polycrystalline SiC substrate; and an interface layer sandwiched between the first substrate and the second substrate and comprising at least elements of phosphorus and chromium.

A semiconductor device has a first substrate made of a first semiconductor material, such as silicon. A sacrificial layer is formed over a first surface of the first substrate. A seed layer is formed over the sacrificial layer. A compliant layer is formed over a second surface of the first substrate opposite the first surface of the first substrate. A first semiconductor layer made of a second semiconductor material, such as silicon carbide, dissimilar from the first semiconductor material is formed over the sacrificial layer. The first substrate and sacrificial layer are removed leaving the first semiconductor layer substantially defect-free. The first semiconductor layer containing the second semiconductor material is formed at a temperature greater than a melting point of the first semiconductor material. A second semiconductor layer is formed over the first semiconductor layer with an electrical component formed in the second semiconductor layer.

A method of cleaning a wafer comprises: a scrubbing operation comprising treating a target wafer to be cleaned with a brush at a rotation rate of 200 rpm or less to prepare a brush cleaned wafer; and a cleaning operation comprising cleaning the brush cleaned wafer with a cleaning solution to prepare a cleaned bare wafer, wherein the cleaning operation comprises a first cleaning operation and a second cleaning operation sequentially.

A SiC semiconductor device includes a SiC chip having a main surface, a trench gate structure formed at the main surface, a trench source structure formed at the main surface away from the trench gate structure in one direction, an insulating film covering the trench gate structure and the trench source structure above the main surface, a gate main surface electrode formed on the insulating film and a gate wiring that is led out from the gate main surface electrode onto the insulating film such as to cross the trench gate structure and the trench source structure in the one direction, and that is electrically connected to the trench gate structure through the insulating film, and that faces the trench source structure with the insulating film between the trench source structure and the gate wiring.

Provided is a surface treatment method for a SiC substrate (40), the method being capable of controlling whether to generate a step bunching or the type of step bunching that is generated. In the surface treatment method in which the surface of the SiC substrate (40) is etched by heating the SiC substrate (40) under Si vapor pressure, an etching mode and an etching depth which are determined at least on the basis of an etching rate, are controlled to etch the SiC substrate (40), so that a surface pattern of the SiC substrate (40) after etching treatment is controlled.

Method for manufacturing a bonded SOI wafer by bonding a bond wafer and base wafer, each composed of a silicon single crystal, via an insulator film, including the steps: depositing a polycrystalline silicon layer on the base wafer bonding surface side, polishing the polycrystalline silicon layer surface, forming the insulator film on the bonding surface of the bond wafer, bonding the polished surface of the base wafer polycrystalline silicon layer and bond wafer via the insulator film; thinning the bonded bond wafer to form an SOI layer; wherein, in the step of depositing the polycrystalline silicon layer, a wafer having a chemically etched surface as base wafer; chemically etched surface is subjected to primary polishing followed by depositing the polycrystalline silicon layer on surface subjected to the primary polishing, and in the step polishing the polycrystalline silicon layer surface, which is subjected to secondary polishing or secondary and finish polishing.

In accordance with the following step of a method of manufacturing a MOSFET, a first cutting step of cutting a silicon carbide wafer along a plane substantially parallel to a {11-20} plane is performed. After the first cutting step, a second cutting step of cutting the silicon carbide wafer along a plane substantially perpendicular to the {11-20} plane and substantially perpendicular to the first main surface is performed.