The present disclosure relates to a semiconductor structure that includes a well region and a semiconductor substrate. The well region is disposed within the semiconductor substrate. The well region includes a plurality of first regions separated by a plurality of second regions, where the plurality of first regions is of a first doping and the plurality of second regions are of a second doping different than the first doping. A gate electrode overlies the well region where the gate electrode is disposed laterally over a portion of the plurality of first regions and a portion of the plurality of second regions.

A semiconductor device includes a semiconductor substrate, a transistor section, a diode section, and a boundary section provided between the transistor section and the diode section in the semiconductor substrate. The transistor section has gate trench portions which are provided from an upper surface of the semiconductor substrate to a position deeper than that of an emitter region, and to each of which a gate potential is applied. An upper-surface-side lifetime reduction region is provided on the upper surface side of the semiconductor substrate in the diode section and a partial region of the boundary section, and is not provided in a region that is overlapped with the gate trench portion in the transistor section in a surface parallel to the upper surface of the semiconductor substrate.

The present technology relates to a solid-state imaging device and electronic equipment to suppress degradation of Dark characteristics. A photoelectric converting unit configured to perform photoelectric conversion, and a PN junction region including a P-type region and an N-type region on a side of a light incident surface of the photoelectric converting unit are included. Further, on a vertical cross-section, the PN junction region is formed at three sides including a side of the light incident surface among four sides enclosing the photoelectric converting unit. Further, a trench which penetrates through a semiconductor substrate in a depth direction and which is formed between the photoelectric converting units each formed at adjacent pixels is included, and the PN junction region is also provided on a side wall of the trench. The present technology can be applied, for example, to a backside irradiation type CMOS image sensor.

A semiconductor device comprises: a substrate; a well region provided in the substrate, having a second conductivity type; source regions having a first conductivity type; body tile regions having the second conductivity type, the source regions and the body tie regions being alternately arranged in a conductive channel width direction so as to form a first region extending along the conductive channel width direction, and a boundary where the edges of the source regions and the edges of the body tie regions are alternately arranged being formed on two sides of the first region; and a conductive auxiliary region having the first conductivity type, provided on at least one side of the first region, and directly contacting the boundary, a contact part comprising the edge of at least one source region on the boundary and the edge of at least one body tie region on the boundary.

A chip-scale sensor package structure includes a sensor chip, a first package body surrounding and connected to an outer lateral side of the sensor chip, a ring-shaped support disposed on a top side of the first package body, a light permeable member disposed on the ring-shaped support, and a redistribution layer (RDL) disposed on a bottom surface of the sensor chip and a bottom side of the first package body. The sensor chip includes a sensing region arranged on the top surface thereof, a plurality of internal contacts, and a plurality of conductive paths respectively connected to the internal contacts and electrically coupled to the sensing region. The sensing region is spaced apart from the ring-shaped support by a distance less than 300 μm. A bottom surface of the RDL has a plurality of external contacts electrically coupled to the internal contacts.

A chip-scale sensor package structure includes a sensor chip, a first package body surrounding and connected to an outer lateral side of the sensor chip, a ring-shaped support disposed on a top side of the first package body, a light permeable member disposed on the ring-shaped support, and a redistribution layer (RDL) disposed on a bottom surface of the sensor chip and a bottom side of the first package body. The sensor chip includes a sensing region arranged on the top surface thereof, a plurality of internal contacts, and a plurality of conductive paths respectively connected to the internal contacts and electrically coupled to the sensing region. The sensing region is spaced apart from the ring-shaped support by a distance less than 300 μm. A bottom surface of the RDL has a plurality of external contacts electrically coupled to the internal contacts.

A display device includes a display panel, a printed circuit board attached to the display panel and including a ground potential supply terminal, a circuit, and a wiring pattern electrically coupling the ground potential supply terminal and the circuit, and a housing that contacts a coupling place provided to the wiring pattern and is attached to the printed circuit board through the coupling place. The wiring pattern includes a terminal wiring pattern electrically coupled with the ground potential supply terminal, a circuit wiring pattern branched from a branch part at a predetermined position on the terminal wiring pattern and electrically coupled with the circuit, and a housing wiring pattern branched from the branch part of the terminal wiring pattern and electrically coupled with the coupling place, and the circuit wiring pattern and the housing wiring pattern are uncoupled with each other at any place other than the branch part.

A semiconductor device includes: an n-doped drift region between first and second surfaces of a semiconductor body; a p-doped first region at the second surface; and an n-doped field stop region between the drift and first region. The field stop region includes first and second sub-regions with hydrogen related donors. A p-n junction separates the first region and first sub-region. A concentration of the hydrogen related donors, along a first vertical extent of the first sub-region, steadily increases from the pn-junction to a maximum value, and steadily decreases from the maximum value to a reference value at a first transition between the sub-regions. A second vertical extent of the second sub-region ends at a second transition to the drift region where the concentration of hydrogen related donors equals 10% of the reference value. A maximum concentration value in the second sub-region is at most 20% larger than the reference value.

Plural sessions of proton irradiation are performed by differing ranges from a substrate rear surface side. After first to fourth n-type layers of differing depths are formed, the protons are activated. Next, helium is irradiated to a position deeper than the ranges of the proton irradiation from the substrate rear surface, introducing lattice defects. When the amount of lattice defects is adjusted by heat treatment, protons not activated in a fourth n-type layer are diffused, forming a fifth n-type layer contacting an anode side of the fourth n-type layer and having a carrier concentration distribution that decreases toward the anode side by a more gradual slope than that of the fourth n-type layer. The fifth n-type layer that includes protons and helium and the first to fourth n-type layers that include protons constitute an n-type FS layer. Thus, a semiconductor device having improved reliability and lower cost may be provided.

An electronic apparatus is provided and includes a first substrate comprising a first conductive layer; a second substrate which is opposed to the first conductive layer and is separated from the first conductive layer, the second substrate including a second conductive layer, and a first hole penetrating the second substrate; and a connecting material which electrically connects the first conductive layer and the second conductive layer via the first hole, wherein the connecting material consists of a single material; and the second conductive layer is located on the second substrate on a side opposite to a side that is opposed to the first conductive layer.