A semiconductor device package includes a substrate and a shielding layer. The substrate has a first surface, a second surface opposite to the first surface and a first lateral surface extending between the first surface and the second surface. The substrate has an antenna pattern disposed closer to the second surface than the first surface. The shielding layer extends from the first surface toward the second surface of the substrate. The shielding layer covers a first portion of the first lateral surface adjacent to the first surface of the substrate. The shielding layer exposes a second portion of the first lateral surface adjacent to the second surface of the substrate.

A component carrier includes a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure. The at least one electrically conductive layer structure includes a first trace. A tapering trench is formed in the at least one electrically insulating layer structure beside and below the first trace. A method of manufacturing the component carrier is also described.

An array substrate and a manufacturing method therefor, a display panel, and a backlight module, are provided. The array substrate may comprise a base substrate, a metal wiring layer, a first planarization layer, an electrode layer, a second planarization layer, and a functional device layer stacked in sequence. The electrode layer comprises a metal sub-layer and a conductive sub-layer stacked on one side of the base substrate in sequence; the material of the metal sub-layer comprises a metal or a metal alloy; the conductive sub-layer has an oxidation resistance and covers the metal sub-layer . The functional device layer is disposed on the side of the second planarization layer distant from the base substrate, and comprises a plurality of functional devices electrically connected to the electrode layer.

A package substrate of a semiconductor package includes conductive lines of a first layer disposed on a first surface of a base layer and conductive lines of a second layer disposed on a second surface of the base layer. An opening hole located between a first remaining portion and a second remaining portion to separate the first and second remaining portions from each other. The first remaining portion is electrically connected to a first conductive line among the conductive lines of the second layer, and the second remaining portion is electrically connected to a second conductive line among the conductive lines of the second layer.

An integrated circuit includes a resistive material layer formed on a substrate, a metal layer formed on the resistive material layer, a bipolar transistor formed on the substrate, and a resistive element formed on the substrate. The bipolar transistor includes, as a sub-layer, the metal layer formed in a first region, and also includes a collector layer formed on the sub-collector layer. The resistive element is constituted by the resistive material layer formed in a second region.

A 3D-IC includes a first tier device and a second tier device. The first tier device and the second tier device are vertically stacked together. The first tier device includes a first substrate and a first interconnect structure formed over the first substrate. The second tier device includes a second substrate, a doped region formed in the second substrate, a dummy gate formed over the substrate, and a second interconnect structure formed over the second substrate. The 3D-IC also includes an inter-tier via extends vertically through the second substrate. The inter-tier via has a first end and a second end opposite the first end. The first end of the inter-tier via is coupled to the first interconnect structure. The second end of the inter-tier via is coupled to one of: the doped region, the dummy gate, or the second interconnect structure.

A method of forming integrated power electronics packages by 3D-printing the PCB on and around power devices includes bonding a power device to a first surface of a cold plate and printing, using a 3D-printer, a circuit board on and around the power devices such that the circuit board includes one or more insulating portions and one or more conductive portions.

A circuit assembly may include a substrate and a pattern of contact points formed from deformable conductive material supported by the substrate. The assembly may further include an electric component supported by the substrate and having terminals arranged in a pattern corresponding to the pattern of contacts points. The one or more of the terminals of the electric component may contact one or more of the corresponding contact points to form one or more electrical connections between the electric component and the contact points.

A method of joining a metal-ceramic substrate having metalization on at least one side to a metal body by using a metal alloy is disclosed. The metal body has a thickness of less than 1.0 mm, and the metal alloy contains aluminum and has a liquidus temperature of greater than 450° C. The resulting metal-ceramic module provides a strong bond between the metal body and the ceramic substrate. The resulting module is useful as a circuit carrier in electronic appliances, with the metal body preferably functioning as a cooling body.

The present invention relates to an improved electronic circuit, as well as an improved substrate with electronic circuits, with an identification pattern. The invention makes it possible to make them identifiable and amongst other things to retrace the circuit(s) in this way through the production process. Furthermore, the invention relates to an improved production method for circuits and substrates according to the invention.