A method of processing a warped workpiece includes a warpage eliminating step of applying a laser beam whose wavelength is transmittable through the workpiece to the workpiece while positioning a focused spot of the laser beam in the workpiece at a predetermined first position thicknesswise across the workpiece, thereby forming modified layers in the workpiece and cracks extending from the modified layers to a lower surface of the workpiece along all of projected dicing lines on the workpiece, thereby eliminating the warpage from the workpiece, and a modified layer forming step of, after the warpage eliminating step, applying the laser beam to the workpiece while positioning the focused spot of the laser beam in the workpiece at a position above the first position away from the lower surface of the workpiece, thereby forming modified layers in the workpiece along the projected dicing lines.

A method for processing semiconductor wafers includes obtaining measurement data from a surface of a semiconductor wafer processed by a front-end process tool. The method includes determining a center plane of the wafer based on the measurement data, generating raw shape profiles, and generating ideal shape profiles. The method further includes generating Gapi profiles based on the raw shape profiles and the ideal shape profiles, and calculating a Gapi value of the semiconductor wafer based on the Gapi profiles. The generated Gapi profiles and/or the calculated Gapi value may be used to tune the front-end process tool and/or sort the semiconductor wafer for polishing. Systems include at least a front-end process tool, a flatness measurement tool, and a computing device.

A processing condition specifying method that includes Steps S31, S32, and S33. In Step S31, a prediction thickness information piece containing prediction values of thicknesses after processing on the substrate W is calculated for each of a plurality of recipe information pieces based on measurement thickness information containing measurement values of thicknesses of the substrate W. In Step S32, the prediction thickness information pieces each calculated for a corresponding one of the recipe information pieces are evaluated according to a prescribed evaluation method and a prediction thickness information piece is selected from among the prediction thickness information pieces. In Step S33, a recipe information piece corresponding to the selected prediction thickness information piece is specified. The measurement values contained in the measurement thickness information indicate a thickness of the substrate W measured before processing on the substrate W.

A method for processing semiconductor wafers includes obtaining measurement data of an edge profile of a semiconductor wafer processed by a front-end process tool. The method includes determining an edge profile center point based on the measurement data, generating a raw height profile, and generating an ideal edge profile. The method further includes generating a Gapi edge profile of the semiconductor wafer based on the raw height profile and the ideal edge profile and calculating a Gapi edge value of the semiconductor wafer based on the Gapi edge profile. The generated Gapi edge profile and/or the calculated Gapi edge value may be used to tune the front-end process tool and/or sort the semiconductor wafer for polishing. Systems include at least a front-end process tool, a flatness measurement tool, and a computing device.

A storage apparatus for storing an object includes a load port unit that a receptacle is loaded onto or unloaded from, in which the receptacle accommodates the object in a storage space formed by a body and a cover that covers the body, and a controller. The load port unit includes a housing having an interior space, a stage member that is provided on the housing and that opens the storage space by moving the body, the receptacle being seated on the stage member, and an exhaust tube that evacuates a spacing space between the body and the cover spaced apart from each other. One end of the exhaust tube faces toward the spacing space, and an opposite end of the exhaust tube faces toward the interior space.

Methods and systems for controlling pressure in a cavity of a light source are provided. One system includes a barometric pressure sensor configured for measuring pressure in a cavity of a light source. The system also includes one or more gas flow elements configured for controlling an amount of one or more gases in the cavity. In addition, the system includes a control subsystem configured for comparing the measured pressure to a predetermined range of values for the pressure and, when the measured pressure is outside of the predetermined range, altering a parameter of at least one of the one or more gas flow elements based on results of the comparing.

A semiconductor device includes: a semiconductor substrate; an upper surface electrode formed on an upper surface side of the semiconductor substrate; an insulating film formed on the upper surface side of the semiconductor substrate; and a lower surface electrode formed on a lower surface side of the semiconductor substrate and having a larger area than that of the upper surface electrode, wherein the upper surface electrode and the lower surface electrode are electrodes having a compressive stress.

In a processing apparatus, a vibration detecting unit includes a light source, an interference unit configured to apply light emitted from the light source to a measurement target member and generate an interference pattern image. A control unit includes a storage section configured to store a first interference pattern image captured at a predetermined timing by the imaging unit and a second interference pattern image captured at a timing different from the timing of the first interference pattern image by the imaging unit, a comparing section configured to compare the first interference pattern image and the second interference pattern image stored in the storage section with each other, and a vibration detecting section configured to detect vibration on the basis of the first interference pattern image and the second interference pattern image compared with each other by the comparing section.

The invention is a cost effective multisite parallel wafer tester that has an array of stationary wafer test sites; a single mobile wafer handling and alignment carriage that holds a wafer handling robot, a wafer rotation pre-alignment assembly, a wafer alignment assembly, a wafer front opening unified pod (FOUP), and a wafer camera assembly; and a robot that moves the wafer handling and alignment carriage to and from each test site. Each test site contains a wafer probe card assembly and a floating chuck. In use, wafers are loaded from a front opening FOUP into a wafer buffer FOUP from which wafers are retrieved by the wafer handling and alignment assembly. The robot positions the wafer handling and alignment carriage and the associated wafer handling robot, the wafer rotation pre-alignment assembly, the wafer alignment assembly, the wafer FOUP, and the wafer camera assembly in front of and inside a given test site and aligns the wafer to be tested with the probe card inside the test site using the floating chuck.

An apparatus includes a first and second stages. The first and second stages respectively hold a first and second substrates. The second stage being opposed to the first stage. A stress application portion applies a stress to the first substrate based on a first magnification value. A calculator calculates the first magnification value based on a flatness of the first substrate and a first equation. The first equation represents a relation between flatness of a third substrate, a second magnification value, and an amount of pattern misalignment between the third substrate and a fourth substrate bonded to the third substrate. A controller controls the stress application portion to apply a stress to the first substrate on the first stage based on the first magnification value while the first and second substrates are bonded to each other.