P-type low-concentration regions face bottoms of trenches and extend in a longitudinal direction (first direction) of the trenches. The p-type low-concentration regions are adjacent to one another in a latitudinal direction (second direction) of the trenches and connected at predetermined locations by p-type low-concentration connecting portions that are scattered along the first direction and separated from one another by an interval of at least 3 μm. The p-type low-concentration regions and the p-type low-concentration connecting portions have an impurity concentration in a range of 3×10.sup.17/cm.sup.3 to 9×10.sup.17/cm.sup.3. A depth from the bottoms of the trenches to lower surfaces of the p-type low-concentration regions is in a range of 0.7 μm to 1.1 μm. Between the bottom of each of the trenches and a respective one of the p-type low-concentration regions, a p.sup.+-type high-concentration region is provided. Each p.sup.+-type high-concentration region has an impurity concentration that is at least 2 times the impurity concentration of the p-type low-concentration regions.

Methods may include providing a device structure including a well formed in an epitaxial layer, and forming a plurality of shielding layers in the device structure, wherein at least one shielding layer is formed between a pair of adjacent sacrificial gates of a plurality of sacrificial gates. The method may further include forming a contact over the at least one shielding layer, forming a fill layer over the contact, and forming a plurality of trenches into the device structure, wherein at least one trench of the plurality of trenches is formed between a pair of adjacent shielding layers of the plurality of shielding layers, and wherein the at least one trench of the plurality of trenches is defined in part by a sidewall of the fill layer. The method may further include forming a gate structure within the at least one trench of the plurality of trenches.

Embodiments of the disclosure provide a semiconductor structure and a method for forming the same. The semiconductor structure includes: a semiconductor substrate including a plurality of active areas and first isolation structures arranged at intervals along a first direction; gate structures located in the active areas and the first isolation structures. Top surfaces of the active areas extend beyond top surfaces of the gate structures; second isolation structures with a preset height located on surfaces of the gate structures, and the top surfaces of the second isolation structures are flush with the top surfaces of the active areas.

A semiconductor device includes a semiconductor base body, and a first main electrode and a second main electrode provided on the semiconductor base body. The semiconductor base body includes a drift region of a first conductivity type through which a main current flows, a column region of a second conductivity type arranged adjacent to the drift region in parallel to a current passage of the main current, a second electrode-connection region of the first conductivity type electrically connected to the second main electrode, and a low-density electric-field relaxation region of the first conductivity type having a lower impurity concentration than the drift region and arranged between the second electrode-connection region and the column region.

To provide a composite substrate whereby a nanocarbon film having no defect can be manufactured at low cost.

A method for manufacturing a composite substrate, including: implanting ion from a surface of a single crystal silicon carbide substrate to form an ion-implanted region; bonding an ion-implanted surface of the single crystal silicon carbide substrate and a main surface of a handle substrate, and peeling the single crystal silicon carbide substrate at the ion-implanted region to transfer single crystal silicon carbide thin film onto the handle substrate, wherein the surface to be bonded of the single crystal silicon carbide substrate and the surface to be bonded of the handle substrate each has a surface roughness RMS of 1.00 nm or less.

In a semiconductor device, a source region is made of an epitaxial layer so as to reduce variation in thickness of a base region and variation in a threshold value. Outside of a cell part, a side surface of a gate trench is inclined relative to a normal direction to a main surface of a substrate, as compared with a side surface of a gate trench in the cell part that is provided by the epitaxial layer of the source region being in contact with the base region.

The present disclose relates to a SiC MOSFET device and a manufacturing method thereof. The method includes providing a semiconductor base of a first doping type; forming a patterned first barrier layer on an upper surface; forming a source region extending from the upper surface to the interior of the semiconductor base by taking the first barrier layer as a mask, wherein the source region is of the first doping type; etching a part of the first barrier layer to form a second barrier layer, and allowing anion implantation window of the second barrier layer to be larger than the ion implantation window of the first barrier layer; forming a first type base region by taking the second barrier layer as a mask, wherein the first type base region is of a second doping type; and forming a contact region of the second doping type.

Provided is a SiC substrate treatment method for, with respect to a SiC substrate (40) that has, on its surface, grooves (41), activating ions while preventing roughening of the surface of the substrate. In the method, an ion activation treatment in which the SiC substrate (40) is heated under Si vapor pressure is performed to the SiC substrate (40) has, on its surface, an ion implantation region (46) in which ions have been implanted, and has the grooves (41) provided in a region including at least the ion implantation region (46), thereby ions that are implanted in the SiC substrate (40) is activated while etching the surface of the substrate.

A transistor cell including a semiconductor substrate, which has a front side and a rear side, the front side being situated opposite the rear side. An epitaxial layer is situated on the front side. Channel regions are situated on the epitaxial layer. Source regions are situated on the channel regions. A trench and field shielding regions extending from the front side of the semiconductor substrate into the epitaxial layer, the field shielding regions each being situated laterally spaced apart from the trench and the trench having a shallower depth than the field shielding regions. An implanted expansion region having a particular thickness is situated below the trench.

A MOSFET transistor device includes a functional layer of silicon carbide, having a first conductivity type. Gate structures are formed on a top surface of the functional layer and each includes a dielectric region and an electrode region. Body wells having a second conductivity type are formed within the functional layer, and the body wells are separated from one another by surface-separation regions. Source regions having the first conductivity type are formed within the body wells, laterally and partially underneath respective gate structures. Modified-doping regions are arranged in the surface-separation regions centrally thereto, underneath respective gate structures, in particular underneath the corresponding dielectric regions, and have a modified concentration of dopant as compared to the concentration of the functional layer.