The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The manufacturing method of a semiconductor structure includes: providing a substrate, where a plurality of contact pads are formed on the substrate; depositing a dielectric layer on the substrate, where the dielectric layer fills gaps between the contact pads and covers the contact pads; and etching the dielectric layer through a plasma etching process to expose the contact pads, where an etching gas used in the plasma etching process includes an oxygen-free etching gas. The manufacturing method can avoid the formation of metal oxides on the contact pads, and avoid residual conductive metal particles or metal compounds on surfaces of the contact pads and the adjacent dielectric layers, which is beneficial to ensure the electrical performance of the semiconductor structure, thereby improving the use reliability of the semiconductor structure.

A method includes forming a plurality of dielectric layers, forming a lower portion of a seal ring including a plurality of metal layers, each extending into one of the plurality of dielectric layers, depositing a first passivation layer over the plurality of dielectric layers, forming an opening in the first passivation layer, forming a via ring in the opening and physically contacting the lower portion of the seal ring, and forming a metal ring over the first passivation layer and joined to the via ring. The via ring and the metal ring form an upper portion of the seal ring. The metal ring includes an edge portion having a zigzag pattern. The method further includes forming a second passivation layer on the metal ring, and performing a singulation process to form a device die, with the seal ring being proximate edges of the device die.

Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure includes a semiconductor substrate having a first trench, and a trench isolation region positioned in the first trench. The trench isolation region contains a dielectric material, the trench isolation region includes a second trench surrounded by the dielectric material, and the trench isolation region includes openings that penetrate through the dielectric material. A semiconductor layer is positioned in the second trench of the trench isolation region. The semiconductor layer contains a single-crystal semiconductor material.

A structure for radiofrequency applications includes: a semiconducting supporting substrate, and a trapping layer arranged on the supporting substrate. The trapping layer includes a higher defect density than a predetermined defect density. The predetermined defect density is the defect density beyond which the electric resistivity of the trapping layer is no lower 10,000 ohm.Math.cm over a temperature range extending from −20° C. to 120° C.

The present application provides a process for preparing an epitaxy wafer, and an epitaxy wafer prepared therefrom. The process comprises: step S1: providing a semiconductor substrate wafer, conducting an epitaxy process and forming an epitaxy layer on the wafer; and step S2: conducting a thermal treatment to the wafer to eliminate the haze pattern of the epitaxy layer. According to the process, the thermal treatment after the epitaxy process can facilitate the orientation of atoms on the wafer surface toward the lowest energy orientation, so that the atoms of the epitaxy layer arrange and accumulate uniformly. Therefore, the haze pattern on the wafer surface can be eliminated.

Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure includes a semiconductor substrate having a first trench, and a trench isolation region positioned in the first trench. The trench isolation region contains a dielectric material, the trench isolation region includes a second trench surrounded by the dielectric material, and the trench isolation region includes openings that penetrate through the dielectric material. A semiconductor layer is positioned in the second trench of the trench isolation region. The semiconductor layer contains a single-crystal semiconductor material.

Structures and methods for making nanosheet structures with an electrically isolating feature associated therewith. The structure includes: a substrate, an epitaxial oxide layer over the substrate, a plurality of stacked nanosheets of semiconductor channel material over the epitaxial layer, and a source/drain semiconductor material located laterally adjacent and on each side of the plurality of stacked nanosheets of semiconductor channel material, where the plurality of nanosheets are decoupled from the source/drain semiconductor material by the epitaxial oxide layer.

Examples herein describe techniques for isolating portions of an IC that include sensitive components (e.g., inductors or capacitors) from return current in a grounding plane. An output current generated by a transmitter or driver in an IC can generate a magnetic field which induces return current in the grounding plane. If the return current is proximate the sensitive components, the return current can inject noise which can negatively impact other components in the IC. To isolate the sensitive components from the return current, embodiments herein include forming slots through the grounding structure which includes the grounding plane on one or more sides of the sensitive components.

A thin layer of lattice matched wide bandgap semiconductor material having semi-insulating properties is employed as an isolation layer between the substrate and a vertical stack of suspended semiconductor channel material nanosheets. The presence of such an isolation layer eliminates the parasitic leakage path between the source region and the drain region that typically occurs through the substrate, while not interfering with the CMOS device that is formed around the semiconductor channel material nanosheets.

A thin layer of lattice matched wide bandgap semiconductor material having semi-insulating properties is employed as an isolation layer between the substrate and a vertical stack of suspended semiconductor channel material nanosheets. The presence of such an isolation layer eliminates the parasitic leakage path between the source region and the drain region that typically occurs through the substrate, while not interfering with the CMOS device that is formed around the semiconductor channel material nanosheets.