A semiconductor memory device according to an embodiment includes: a stacked body in which a plurality of first conductive layers and a plurality of first insulating layers are alternately stacked one by one and includes a stepped portion in which, a first pillar disposed in the stepped portion, the first pillar extending in a stacking direction of the stacked body; and a second pillar extending in the stacking direction within the stacked body, the second pillar forming a memory cell at each intersection with at least a part of the plurality of first conductive layers. The first pillar has a semiconductor layer or a second conductive layer extending in the stacking direction and serving as a core material of the first pillar, and a second insulating layer covering a side wall of the semiconductor layer or the second conductive layer and serving as a liner layer of the first pillar.

Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming a first etch stop layer from a portion of a gate mask, the gate mask extending between spacers adjacent a gate electrode, the gate electrode overlying a semiconductor fin. The method further includes forming a second etch stop layer adjacent the first etch stop layer, forming an opening through the second etch stop layer, and exposing the first etch stop layer by performing a first etching process. The method further includes extending the opening through the first etch stop layer and exposing the gate electrode by performing a second etching process. Once the gate electrode has been exposed, the method further includes forming a gate contact in the opening.

A method for forming a stacked transistor includes forming a sacrificial cap over a first interconnect of a lower level transistor. The method further includes forming an upper level transistor above the sacrificial cap. The method further includes removing the sacrificial cap to form an opening such that the opening is delimited by the upper level transistor. The method further includes forming a second interconnect in the opening such that the second interconnect is in direct contact with the first interconnect.

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier by conducting material that is in a lowest of the conductive tiers and that is directly against multiple of the channel-material strings. The channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. A wall in the lowest conductive tier is aside the conducting material. The wall is in a region that is edge-of-plane relative to the memory plane. The edge-of-plane region comprises a TAV region. The wall is horizontally-elongated relative to an edge of the TAV region that is in the edge-of-plane region. Other memory arrays and methods are disclosed.

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. The conductor tier is directly above a lower tier that comprises conductive lines that are horizontally elongated. An insulator tier is vertically between the conductor tier and the lower tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple to the conductor material of the conductor tier. A through-array-via (TAV) region comprises TAVs that individually directly electrically couple to one of the conductive lines. Insulator walls are in the TAV region. The insulator walls extend vertically through the conductor tier and the insulator tier to the lower tier and are horizontally elongated. Methods are also disclosed.

A method comprises forming a gate structure between gate spacers; etching back the gate structure to fall below top ends of the gate spacers; forming a gate dielectric cap over the etched back gate structure; performing an ion implantation process to form a doped region in the gate dielectric cap; depositing a contact etch stop layer over the gate dielectric cap and an ILD layer over the contact etch stop layer; performing a first etching process to form a gate contact opening extending through the ILD layer and terminating prior to reaching the doped region of the gate dielectric cap; performing a second etching process to deepen the gate contact opening, wherein the second etching process etches the doped region of the gate dielectric cap at a slower etch rate than etching the contact etch stop layer; and forming a gate contact in the deepened gate contact opening.

The present disclosure describes a method for the fabrication of ruthenium conductive structures over cobalt conductive structures. In some embodiments, the method includes forming a first opening in a dielectric layer to expose a first cobalt contact and filling the first opening with ruthenium metal to form a ruthenium contact on the first cobalt contact. The method also includes forming a second opening in the dielectric layer to expose a second cobalt contact and a gate structure and filling the second opening with tungsten to form a tungsten contact on the second cobalt contact and the gate structure. Further, the method includes forming a copper conductive structure on the ruthenium contact and the tungsten contact, where the copper from the copper conductive structure is in contact with the ruthenium metal from the ruthenium contact.

A method includes forming a gate structure over a substrate; forming a source/drain region adjacent the gate structure; forming a first interlayer dielectric (ILD) over the source/drain region; forming a contact plug extending through the first ILD that electrically contacts the source/drain region; forming a silicide layer on the contact plug; forming a second ILD extending over the first ILD and the silicide layer; etching an opening extending through the second ILD and the silicide layer to expose the contact plug, wherein the silicide layer is used as an etch stop during the etching of the opening; and forming a conductive feature in the opening that electrically contacts the contact plug.

A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure comprises at least one two-dimensional (2D) conductive structure; a dielectric layer disposed on the 2D conductive structure; and at least one interconnect structure disposed in the dielectric layer and extending into the 2D conductive structure, wherein the interconnect structure laterally connects to at least one edge of the 2D conductive structure.

A semiconductor device includes a lower insulating film that includes a first and second trenches on a substrate, a first wiring in the first trench, a second wiring in the second trench, a capping insulating film including an insulating recess portion and an insulating liner portion, an upper insulating film on the capping insulating film, and an upper contact that penetrates the capping insulating film and connects to the first wiring, The insulating recess portion is in the second trench and the insulating liner portion extends along an upper surface of the lower insulating film. The upper contact includes a contact recess portion in the first trench, an extended portion connected to the contact recess portion, and a plug portion connected to the extended portion inside the upper insulating film. A width of the extended portion is greater than a width of the plug portion.