A method includes depositing a first dielectric layer over a first conductive feature, depositing a first mask layer over the first dielectric layer, and depositing a second mask layer over the first mask layer. A first opening is patterned in the first mask layer and the second mask layer, the first opening having a first width. A second opening is patterned in a bottom surface of the first opening, the second opening extending into the first dielectric layer, the second opening having a second width. The second width is less than the first width. The first opening is extended into the first dielectric layer and the second opening is extended through the first dielectric layer to expose a top surface of the first conductive feature.

A method includes forming a first conductive feature in a first dielectric layer, forming a first metal cap over and contacting the first conductive feature, forming an etch stop layer over the first dielectric layer and the first metal cap, forming a second dielectric layer over the etch stop layer; and etching the second dielectric layer and the etch stop layer to form an opening. The first conductive feature is exposed to the opening. The method further includes selectively depositing a second metal cap at a bottom of the opening, forming an inhibitor film at the bottom of the opening and on the second metal cap, selectively depositing a conductive barrier in the opening, removing the inhibitor film, and filling remaining portions of the opening with a conductive material to form a second conductive feature.

Metal-insulator-metal (MIM) capacitor, an integrated semiconductor device having a MIM capacitor and methods of making. The MIM capacitor includes a first metal layer, a second metal layer and a dielectric layer located between the second metal layer and the first metal layer. The first metal layer, the second metal layer and the dielectric layer may be formed in a comb structure, wherein the comb structure include a first tine structure and at least a second tine structure.

An interconnect structure includes a substrate, a dielectric layer on the substrate, a metal interconnect layer in the dielectric layer and in contact with the substrate, the metal interconnect layer having an upper surface flush with an upper surface of the dielectric layer, and a graphene layer on the metal interconnect layer. The graphene layer insulates a metal from air and prevents the metal from being oxidized by oxygen in the air, thereby increasing the queue time for the CMP process and the device reliability.

A method of forming a mask layout includes forming a layout of a first mask including a lower wiring structure pattern and a dummy lower wiring structure pattern. A layout of a second mask overlapping the first mask and including an upper wiring structure pattern and a dummy upper wiring structure pattern is formed. A layout of a third mask including a first via structure pattern and a first dummy via structure pattern is formed. A layout of a fourth mask including a second via structure pattern and a second dummy via structure pattern is formed. The second via structure pattern may commonly overlap the lower wiring structure pattern and the upper wiring structure pattern, and the second dummy via structure pattern may commonly overlap the dummy lower wiring structure pattern and the dummy upper wiring structure pattern. The fourth mask may overlap the third mask.

A method of forming a semiconductor device includes forming a plurality of non-insulator structures on a substrate, the plurality of non-insulator structures being spaced apart by trenches, forming a sacrificial layer overfilling the trenches, reflowing the sacrificial layer at an elevated temperature, wherein a top surface of the sacrificial layer after the reflowing is lower than a top surface of the sacrificial layer before the reflowing, etching back the sacrificial layer to lower the top surface of the sacrificial layer to fall below top surfaces of the plurality of non-insulator structures, forming a dielectric layer on the sacrificial layer, and removing the sacrificial layer to form air gaps below the dielectric layer.

A method and electronic device are provided. The method includes patterning a metal in a first dielectric layer, depositing a first metal layer over the patterned metal, forming a nanowall under the first metal layer such that the nanowall is in contact with the patterned metal in the first dielectric layer, depositing a second dielectric layer on the first dielectric layer, removing at least a portion of the nanowall, thereby forming a channel in the second dielectric layer, and depositing a metal via in the channel such that the metal via is in contact with the patterned metal in the first dielectric layer.

A semiconductor device includes: a lower wiring including: a lower filling film, which extends in a first direction and includes a first portion having a first width in the first direction and a second portion, having a second width smaller than the first width in the first direction, on the first portion; and a lower barrier film which is disposed on a side wall and a bottom surface of the first portion, and is not disposed on a side wall of the second portion in a cross-sectional view of the first direction; and an upper wiring structure including: an upper via connected to the lower wiring; and an upper wiring extending in a second direction intersecting the first direction on the upper via, wherein the upper wiring structure further includes an upper barrier film, and an upper filling film in a trench defined by the upper barrier film, each of the upper via and the upper wiring comprises the upper barrier film and the upper filling film, and the upper via is not separated from the upper wiring by the upper barrier film, and is separated from the second portion of the lower filling film by the upper barrier film.

A method for fabricating a semiconductor device includes: forming a dielectric layer over a substrate; forming a hole-shaped partial via in the dielectric layer; forming a line-shaped trench that partially overlaps with the partial via and has a greater line width than a line width of the partial via in the dielectric layer; forming a hole-shaped via that has a smaller line width than the line width of the partial via and penetrates the dielectric layer on a lower surface of the partial via; and gap-filling the via, the partial via and the trench with a conductive material, wherein a lower surface of the trench is positioned at a higher level than the lower surface of the partial via.

Manufacturing a semiconductor chip based on redefining tolerance rules to create an otherwise prohibited structure including redefining a tolerance rule to permit creation of a minimum area metal trench structure violating the tolerance rule during a routing operation; and fabricating the minimum area metal trench structure on the semiconductor substrate based on the redefined tolerance rule.