Semiconductor device and fabrication method are provided. The method for forming the semiconductor device includes providing a substrate; forming a dielectric layer on the substrate; forming a through hole in the dielectric layer, the through hole exposing a portion of a top surface of the substrate; performing a surface treatment process on the dielectric layer of sidewalls of the through hole; and filling a metal layer in the through hole.

In one exemplary aspect, a method comprises providing a semiconductor structure having a substrate, one or more first dielectric layers over the substrate, a first metal plug in the one or more first dielectric layers, and one or more second dielectric layers over the one or more first dielectric layers and the first metal plug. The method further comprises etching a via hole into the one or more second dielectric layers to expose the first metal plug, etching a top surface of the first metal plug to create a recess thereon, and applying a metal corrosion protectant comprising a metal corrosion inhibitor to the top surface of the first metal plug.

Semiconductor structures having a source contact and a drain contact that exhibit reduced contact resistance and methods of forming the same are disclosed. In one embodiment of the present application, the reduced contact resistance is provided by forming a layer of a dipole metal or metal-insulator-semiconductor (MIS) oxide between an epitaxial semiconductor material (providing the source region and the drain region of the device) and an overlying metal semiconductor alloy. In yet other embodiment, the reduced contact resistance is provided by increasing the area of the source region and drain region by patterning the epitaxial semiconductor material that constitutes at least an upper portion of the source region and drain region of the device.

A method for forming a semiconductor device is provided. The method includes the following steps: providing a semiconductor substrate; forming a pad layer on the semiconductor substrate; forming a first passivation layer on the pad layer; forming a second passivation layer on the first passivation layer, wherein the second passivation layer comprises polycrystalline silicon; forming an oxide layer on the second passivation layer; forming a nitride layer on the oxide layer; removing a portion of the oxide layer and a portion of the nitride layer to expose a portion of the second passivation layer; removing the portion of the second passivation layer that has been exposed to expose a portion of the first passivation layer; and removing the portion of the first passivation layer that has been exposed to expose a portion of the pad layer.

A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.

The present disclosure describes a semiconductor device with a nitrided capping layer and methods for forming the same. One method includes forming a first conductive structure in a first dielectric layer on a substrate, depositing a second dielectric layer on the first conductive structure and the first dielectric layer, and forming an opening in the second dielectric layer to expose the first conductive structure and a portion of the first dielectric layer. The method further includes forming a nitrided layer on a top portion of the first conductive structure, a top portion of the portion of the first dielectric layer, sidewalls of the opening, and a top portion of the second dielectric layer, and forming a second conductive structure in the opening, where the second conductive structure is in contact with the nitrided layer.

Techniques for forming a metastable phosphorous P-doped silicon Si source drain contacts are provided. In one aspect, a method for forming n-type source and drain contacts includes the steps of: forming a transistor on a substrate; depositing a dielectric over the transistor; forming contact trenches in the dielectric that extend down to source and drain regions of the transistor; forming an epitaxial material in the contact trenches on the source and drain regions; implanting P into the epitaxial material to form an amorphous P-doped layer; and annealing the amorphous P-doped layer under conditions sufficient to form a crystalline P-doped layer having a homogenous phosphorous concentration that is greater than about 1.5×10.sup.21 atoms per cubic centimeter (at./cm.sup.3). Transistor devices are also provided utilizing the present P-doped Si source and drain contacts.

A ruthenium film forming method includes: causing chlorine to be adsorbed to an upper portion of a recess at a higher density than to a lower portion of the recess by supplying a chlorine-containing gas to a substrate including an insulating film and having the recess; and forming a ruthenium film in the recess by supplying a Ru-containing precursor to the recess to which the chlorine is adsorbed.

Methods of etching a metal layer and a metal-containing barrier layer to a predetermined depth are described. In some embodiments, the metal layer and metal-containing barrier layer are formed on a substrate with a first dielectric and a second dielectric thereon. The metal layer and the metal-containing barrier layer formed within a feature in the first dielectric and the second dielectric. In some embodiments, the metal layer and metal-containing barrier layer can be sequentially etched from a feature formed in a dielectric material. In some embodiments, the sidewalls of the feature formed in a dielectric material are passivated to change the adhesion properties of the dielectric material.

A method for making a semiconductor device includes patterning at least one dielectric layer disposed over a conductive cap layer to form a via opening penetrating through the at least one dielectric layer to expose the conductive cap layer and to form a top portion of the conductive cap layer into a metal oxide layer; converting the metal oxide layer to a metal oxynitride layer by a soft ashing process using a processing gas containing nitrogen gas; removing the metal oxynitride layer from a remaining portion of the conductive cap layer; and forming a via contact in the via opening to electrically connect the remaining portion of the conductive cap layer.