A semiconductor device includes a first gate structure and a second gate structure over a fin, a dielectric cut pattern sandwiched by the first and second gate structures, and a liner layer surrounding the dielectric cut pattern. The dielectric cut pattern is spaced apart from the fin and extends further from the substrate than a first gate electrode of the first gate structure and a second gate electrode of the second gate structure. The semiconductor device further includes a conductive feature sandwiched by the first and second gate structures. The conductive feature is divided by the conductive feature into a first segment and a second segment. The first segment of the conductive feature is above a source/drain region of the fin.

A method includes depositing a first dielectric layer over a first conductive feature, depositing a first mask layer over the first dielectric layer, and depositing a second mask layer over the first mask layer. A first opening is patterned in the first mask layer and the second mask layer, the first opening having a first width. A second opening is patterned in a bottom surface of the first opening, the second opening extending into the first dielectric layer, the second opening having a second width. The second width is less than the first width. The first opening is extended into the first dielectric layer and the second opening is extended through the first dielectric layer to expose a top surface of the first conductive feature.

A method of forming a via is provided. A lower metal element is formed, and a first patterned photoresist is used to form a sacrificial element over the lower metal element. A dielectric region including a dielectric element projection extending upwardly above the sacrificial element is formed. A second patterned photoresist including a second photoresist opening is formed, wherein the dielectric element projection is at least partially located in the second photoresist opening. A dielectric region trench opening is etched in the dielectric region. The sacrificial element is removed to define a via opening extending downwardly from the dielectric region trench opening. The dielectric region trench opening and the via opening are filled to define (a) an upper metal element in the dielectric region trench opening and (b) a via in the via opening, wherein the via extends downwardly from the upper metal element.

A method of manufacturing a semiconductor structure and a semiconductor structure are disclosed. The method of manufacturing a semiconductor structure includes: providing a substrate; forming multiple support structures on the substrate, where the multiple support structures are arranged at intervals along a first direction, and a gate trench is formed between every two adjacent support structures; forming a gate structure in the gate trench; and removing a part of each of the support structures, such that each of retained support structures forms two isolation sidewalls spaced apart, the two isolation sidewalls are arranged on opposite sidewalls of the adjacent gate structures respectively, and a filling region is formed by the two isolation sidewalls.

Various embodiments of the present disclosure improve integration degree of semiconductor devices by simultaneously forming interconnections extending in various directions through a single gap-fill process. The embodiments of the present invention provide an interconnection structure that is capable of simplifying semiconductor processing, a semiconductor device including the interconnection structure, and a method for fabricating the semiconductor device. According to an embodiment of the present disclosure, an interconnection structure comprises: a stack of a plurality of interconnections, wherein at least two layers of the plurality of interconnections extend in different directions, and a portion of a top surface of a lower interconnection of the at least two layers is in direct contact with a portion of a bottom surface of an upper interconnection of the at least two layers.

A method includes forming a plurality of first line-shaped mask patterns over a substrate including a memory cell region and an array edge region; forming a plurality of second line-shaped mask patterns over the plurality of first line-shaped mask patterns; removing first portions from the plurality of first line-shaped mask patterns in the memory cell region to leave a plurality of island-shaped mask patterns above the memory cell region; removing second portions from the plurality of first line-shaped mask patterns in the array edge region to leave a holes-provided mask pattern above the array edge region; forming a mask pattern which includes a plurality of holes provided on portions; and forming, with the mask pattern which includes the plurality of holes, a plurality of contact holes in the array edge region to provide a plurality of contact electrodes connected to a plurality of word-lines.

A variety of applications can include apparatus having a memory device with an array of vertical strings of memory cells for the memory device with data lines coupled to the vertical strings, where the data lines have been formed by a metal liner deposition process. In the metal liner deposition, a metal can be formed on a patterned dielectric region. The metal liner deposition process allows for construction of the height of the data lines to be well controlled with selection of a thickness for the dielectric region used in forming the metal liner. Use of a metal liner deposition provides a controlled mechanism to reduce data line capacitance by being able to select liner thickness in forming the data lines. The use of the dielectric region with the metal liner deposition can allow the fabrication of the data lines to avoid pitch double or pitch quad processes.

A method for fabricating a semiconductor device includes: forming a stack body over a substrate; forming channel structures in the stack body, the channel structures comprising a channel layer penetrating the stack body; forming a contact-level dielectric layer over the stack body and the channel structures; forming a contact hole penetrating the contact-level dielectric layer; forming contact plugs in the contact hole, the contact plugs coupled to the channel layers of the channel structures; recessing the contact plugs to form upper surfaces of the contact plugs that are lower than an upper surface of the contact-level dielectric layer; forming a bit line-level dielectric layer including a spacer layer over the recessed contact plugs; etching the bit line-level dielectric layer to form trenches that expose the recessed contact plugs; and forming a bit line in one or more of the trenches.

Embodiments of three-dimensional (3D) memory devices having through array contacts (TACs) and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate comprising a plurality of conductor/dielectric layer pairs, a channel structure extending vertically through the conductor/dielectric layer pairs in the memory stack, a TAC extending vertically through the conductor/dielectric layer pairs in the memory stack, and a dummy channel structure filled with a dielectric layer and extending vertically through the conductor/dielectric layer pairs in the memory stack.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.