Semiconductor device is provided. The semiconductor device includes a base substrate including a first region, a second region, and a third region arranged along a first direction, a first doped layer in the base substrate at the first region and a second doped layer in the base substrate at the third region, a first gate structure on the base substrate at the second region, a first dielectric layer on the base substrate coving the first doped layer, the second doped layer, and sidewalls of the first gate structure, first trenches in the first dielectric layer at the first region and the third region respectively, a first conductive layer in the first trenches, a second conductive layer on a surface of the first conductive layer at the second sub-regions after forming the first conductive layer, and a third conductive layer on the contact region of the first gate structure.

A method of making a semiconductor structure includes depositing a first passivation material between adjacent conductive elements on a substrate, wherein a bottommost surface of the first passivation material is coplanar with a bottommost surface of each of the adjacent conductive elements. The method further includes depositing a second passivation material on the substrate, wherein the second passivation material contacts a sidewall of each of the adjacent conductive elements and a sidewall of the first passivation material, a bottommost surface of the second passivation material is coplanar with the bottommost surface of each of the adjacent conductive elements, and the second passivation material is different from the first passivation material.

A method for manufacturing a semiconductor device includes providing a substrate structure having an action region and a gate structure having a gate dielectric layer, a gate, a hardmask. The method also includes forming a first dielectric layer on the gate structure, forming a second dielectric layer on the first dielectric layer, performing a surface treatment on the second dielectric layer so that the upper surface of the second dielectric layer is flush with the upper surface of the mask member, which has a first recess is in its middle portion, forming a third dielectric layer on the second dielectric layer covering the mask member and selectively etching the third dielectric layer and the second dielectric layer relative to the first dielectric layer and the hardmask to form an opening adjacent to the gate structure and exposing the first dielectric layer on sidewalls of the gate structure.

Methods for filling gaps with dielectric material involve deposition using an atomic layer deposition (ALD) technique to fill a gap followed by deposition of a cap layer on the filled gap by a chemical vapor deposition (CVD) technique. The ALD deposition may be a plasma-enhanced ALD (PEALD) or thermal ALD (tALD) deposition. The CVD deposition may be plasma-enhanced CVD (PECVD) or thermal CVD (tCVD) deposition. In some embodiments, the CVD deposition is performed in the same chamber as the ALD deposition without intervening process operations. This in-situ deposition of the cap layer results in a high throughput process with high uniformity. After the process, the wafer is ready for chemical-mechanical planarization (CMP) in some embodiments.

A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.

Disclosed semiconductor device manufacturing processes improve the flatness of a passivation layer deposited above a redistribution layer (RDL). When a thin passivation layer is deposited above the RDL, its top surface tends to become very uneven due to the large gaps that typically form over the etched portions of the RDL, particularly when the RDL is disposed over an underlying super high density metal-insulator-metal (MIM) capacitor. In order to reduce the incidence of stress concentration areas on the uneven surface, a thicker passivation layer is instead deposited to minimize gap formation therein, and a chemical mechanical planarization (CMP) process is then performed to further smooth the top surface thereof. Reduction of the stress in this manner reduces the incidence of cracking of the underlying MIM, which improves the overall pass rates of semiconductor devices so manufactured.

A semiconductor structure includes a first dielectric layer, a first metallic feature over the first dielectric layer, an air gap over the first dielectric layer and adjacent to the first metallic feature, a second dielectric layer disposed above the air gap and on a sidewall of the first metallic feature, and a third dielectric layer disposed above the air gap and on a sidewall of the second dielectric layer. A lower portion of the first metallic feature is exposed in the air gap. The third and the second dielectric layers are substantially co-planar.

A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.

A method for etching a metal containing feature is provided. Using a pattern mask, layers of material are etched to expose a portion of a metal containing feature. At least a portion of the exposed metal containing feature is etched, and is replaced by the growth of a filler dielectric. The etched portion of the metal containing feature and the filler dielectric reduce the unwanted conductivity between adjacent metal containing features.

Various embodiments of fanout packages are disclosed. A method of forming a microelectronic assembly is disclosed. The method can include bonding a first surface of at least one microelectronic substrate to a surface of a carrier using a direct bonding technique without an intervening adhesive, the microelectronic substrate having a plurality of conductive interconnections on at least one surface of the microelectronic substrate. The method can include applying a molding material to an area of the surface of the carrier surrounding the microelectronic substrate to form a reconstituted substrate. The method can include processing the microelectronic substrate. The method can include singulating the reconstituted substrate at the area of the surface of the carrier and at the molding material to form the microelectronic assembly.