A film forming method includes: providing the substrate into the processing container; forming a metal-based film on the substrate within the processing container; and subsequently, supplying a Si-containing gas into the processing container in a state in which the substrate is provided within the processing container.

Embodiments disclosed herein generally relate to methods of depositing a plurality of layers. A doped copper seed layer is deposited in a plurality of feature definitions in a device structure. A first copper seed layer is deposited and then the first copper seed layer is doped to form a doped copper seed layer, or a doped copper seed layer is deposited directly. The doped copper seed layer leads to increased flowability, reducing poor step coverage, overhang, and voids in the copper layer.

Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor; pre-cleaning the substrate; depositing a titanium silicide (TiSi) layer on the n transistor and on the p transistor by plasma-enhanced chemical vapor deposition (PECVD); optionally depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p transistor; selectively forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the n transistor and the p transistor; forming a second barrier layer on the molybdenum silicide (MoSi) layer; and annealing the semiconductor structure. The method may be performed in a processing chamber without breaking vacuum.

Methods of forming a semiconductor device structure are described. The method includes forming a first conductive feature including a conductive fill material over a substrate, forming an etch stop layer on the conductive fill material, forming an intermetallization dielectric on the etch stop layer, forming an opening in the etch stop layer and the intermetallization dielectric to expose a portion of the conductive fill material, forming a recess in the exposed portion of the conductive fill material, and the opening and the recess together form a rivet-shaped space. The method further includes forming a second conductive feature in the rivet-shaped space and forming a metal nitride layer over the intermetallization dielectric and the second conductive feature. The forming the metal nitride layer includes depositing the metal nitride layer and treating the metal nitride layer with a plasma treatment process.

A method of manufacturing a radio frequency switch includes the steps of: forming a first silicide layer on a second conductive or semiconductor layer; forming a third insulating layer on the first layer; forming a cavity in the third insulating layer reaching the first silicide layer; forming a fourth metal layer in the cavity in contact with the first silicide layer; performing a non-oxidizing annealing; and filling the cavity with a conductive material. The first silicide layer is provided on one or more of the gate, source, and drain of a transistor forming the radio frequency switch.

A semiconductor device includes a device feature. The semiconductor device includes a first silicide layer having a first metal, wherein the first silicide layer is embedded in the device feature. The semiconductor device includes a second silicide layer having a second metal, wherein the second silicide layer, disposed above the device feature, comprises a first portion directly contacting the first silicide layer. The first metal is different from the second metal.

A method for forming an integrated circuit device is provided. The method includes forming a transistor over a frontside of a substrate; forming an interconnect structure over the transistor; depositing a first transition metal layer over the interconnect structure; performing a plasma treatment to turn the first transition metal layer into a first transition metal dichalcogenide layer; forming a dielectric layer over the first transition metal dichalcogenide layer; forming a first gate electrode over the dielectric layer and a first portion of the first transition metal dichalcogenide layer; and forming a first source contact and a first drain contact respectively connected with a second portion and a third portion of the first transition metal dichalcogenide layer, the first portion of the first transition metal dichalcogenide layer being between the second and third portions of the first transition metal dichalcogenide layers.

Embodiments of the present disclosure relate to methods of fabricating conductive features to prevent metal extrusion. Particularly, the conductive feature includes a control layer to reduce grain size of a metal containing layer, thus obtaining a robust structure to decrease extrusion defects. In some embodiments, the control layer is formed between a barrier layer and the conductive feature. In some embodiments, the control layer is formed by adding a control element, such as oxygen, to an upper portion of the barrier layer.

A semiconductor device includes a peripheral circuit region comprising a first substrate, circuit elements on the first substrate, a first insulating layer covering the circuit elements, and a contact plug passing through the first insulating layer and disposed to be connected to the first substrate; and a memory cell region comprising a second substrate, gate electrodes on the second substrate and stacked in a vertical direction, and channel structures passing through the gate electrodes, wherein the contact plug comprises a metal silicide layer disposed to contact the first substrate and having a first thickness, a first metal nitride layer on the metal silicide layer to contact the metal silicide layer and having a second thickness, greater than the first thickness, a second metal nitride layer on the first metal nitride layer, and a conductive layer on the second metal nitride layer.

A device includes a substrate, a dielectric layer over the substrate, and a conductive interconnect in the dielectric layer. The conductive interconnect includes a barrier/adhesion layer and a conductive layer over the barrier/adhesion layer. The barrier/adhesion layer includes a material having a chemical formula MX.sub.n, with M being a transition metal element, X being a chalcogen element, and n being between 0.5 and 2.