An electrode structure with an alloy interface is provided. In one aspect, a method of forming a contact structure includes: patterning a via in a first dielectric layer; depositing a barrier layer onto the first dielectric layer, lining the via; depositing and polishing a first metal layer (Element A) into the via to form a contact in the via; depositing a second metal layer (Element B) onto the contact in the via; annealing the first and second metal layers under conditions sufficient to form an alloy AB; depositing a third metal layer onto the second metal layer; patterning the second and third metal layers into a pedestal stack over the contact to form an electrode over the contact, wherein the alloy AB is present at an interface of the electrode and the contact; and depositing a second dielectric that surrounds the pedestal stack. A contact structure is also provided.

A method may include providing a device structure in the semiconductor device. The device structure may include a buried device contact, a first dielectric layer, disposed over the buried device contact; and a device element, where the device element includes a TiN layer. The method may include implanting an ion species into the TiN layer, wherein the ion species comprises a seed material for selective tungsten deposition.

Described are microelectronic devices comprising a dielectric layer formed on a substrate, a feature comprising a gap defined in the dielectric layer, a barrier layer on the dielectric layer, a two metal liner film on the barrier layer and a gap fill metal on the two metal liner. Embodiments provide a method of forming a microelectronic device comprising the two metal liner film on the barrier layer.

The present disclosure describes a method for the planarization of ruthenium metal layers in conductive structures. The method includes forming a first conductive structure on a second conductive structure, where forming the first conductive structure includes forming openings in a dielectric layer disposed on the second conductive structure and depositing a ruthenium metal in the openings to overfill the openings. The formation of the first conductive structure includes doping the ruthenium metal and polishing the doped ruthenium metal to form the first conductive structure.

A microelectronic device may have side surfaces each including a first portion and a second portion. The first portion may have a highly irregular surface topography extending from an adjacent surface of the microelectronic device. The second portion may have a less uneven surface extending from the first portion to an opposing surface of the microelectronic device. Methods of forming the microelectronic device may include creating dislocations in the wafer in a street between the one or more microelectronic devices by implanting ions and cleaving the wafer responsive to failure of stress concentrations near the dislocations through application of heat, tensile forces or a combination thereof. Related packages and methods are also disclosed.

Described are microelectronic devices and methods for forming interconnections in microelectronic devices. Embodiments of microelectronic devices include tantalum-containing barrier films comprising an alloy of tantalum and a metal dopant selected from the group consisting of ruthenium (Ru), osmium (Os), palladium (Pd), platinum (Pt), and iridium (Ir).

The present disclosure describes a semiconductor device with a diffusion barrier layer on source/drain (S/D) contact structures and a method of fabricating the semiconductor device. The method of fabricating the semiconductor device includes forming a S/D region on a fin structure, forming a S/D contact structure including a metal on the S/D region, forming a barrier layer including silicon and the metal on the S/D contact structure, and forming a via contact structure on the barrier layer. The barrier layer blocks a diffusion of the metal in the S/D contact structure to the via contact structure.

A semiconductor device including a substrate; a fin active region on the substrate and extending in a first direction; a gate structure extending across the fin active region and extending in a second direction; a source/drain region in the fin active region on a side of the gate structure; an insulating structure covering the gate structure and the source/drain region; and contact structures penetrating through the insulating structure and respectively connected to the source/drain region and the gate structure, wherein one of the contact structures includes a seed layer on the gate structure or the source/drain regions and including lower and upper regions, the lower region having a first grain size and the upper region being amorphous or having a grain size different from the first grain size, and a contact plug on an upper region of the seed layer and having a second grain size.

A semiconductor structure, fabrication method and three-dimensional memory are disclosed. A method of fabricating a semiconductor structure includes providing a substrate including a first device region and a second device region; forming a plurality of first recesses in the first device region and a second recess in the second device region, the first recesses and the second recess being formed simultaneously; forming a first isolation trench in the first device region; and forming a second isolation trench in the second device region at a position of the second recess.

A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice layer extending vertically adjacent the at least one trench. The superlattice layer may comprise stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer. Each at least one non-semiconductor monolayer of each group of layers may be constrained within a crystal lattice of adjacent base semiconductor portions. The vertical semiconductor device may also include a doped semiconductor layer adjacent the superlattice layer, and a conductive body adjacent the doped semiconductor layer on a side thereof opposite the superlattice layer and defining a vertical semiconductor device contact.