A method includes forming a first conductive feature in a first dielectric layer, forming a first metal cap over and contacting the first conductive feature, forming an etch stop layer over the first dielectric layer and the first metal cap, forming a second dielectric layer over the etch stop layer; and etching the second dielectric layer and the etch stop layer to form an opening. The first conductive feature is exposed to the opening. The method further includes selectively depositing a second metal cap at a bottom of the opening, forming an inhibitor film at the bottom of the opening and on the second metal cap, selectively depositing a conductive barrier in the opening, removing the inhibitor film, and filling remaining portions of the opening with a conductive material to form a second conductive feature.

The present disclosure relates to the field of semiconductor packaging processes, and provides a semiconductor structure and a forming method thereof. The forming method includes: providing a semiconductor substrate, where a surface of the semiconductor substrate is provided with an exposed conductive structure; forming a passivation layer on the surface of the semiconductor substrate and a surface of the exposed conductive structure; etching the passivation layer to form a recess, where a bottom of the recess exposes one end of the conductive structure; forming an adhesion layer on a surface of the recess; and etching to form a hole in the bottom of the recess.

A method of forming a semiconductor device includes providing a substrate having a patterned film including manganese; depositing a graphene layer over exposed surfaces of the patterned film; depositing a dielectric layer containing silicon and oxygen over the graphene layer; and heat-treating the substrate to form a manganese-containing diffusion barrier region between the graphene layer and the dielectric layer.

A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a conductive line over the substrate. The semiconductor device structure also includes a catalyst structure over the conductive line and a carbon-containing conductive via directly on the catalyst structure. The semiconductor device structure further includes a dielectric layer surrounding the carbon-containing conductive via.

A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.

A metal interconnect structure is doped with zinc, indium, or gallium using top-down doping processes to improve diffusion barrier properties with minimal impact on line resistance. Dopant is introduced prior to metallization or after metallization. Dopant may be introduced by chemical vapor deposition on a liner layer at an elevated temperature prior to metallization, by chemical vapor deposition on a metal feature at an elevated temperature after metallization, or by electroless deposition on a copper feature after metallization. Application of elevated temperatures causes the metal interconnect structure to be doped and form a self-formed barrier layer or strengthen an existing diffusion barrier layer.

A method of depositing a metal material on an isolated seed layer uses a barrier layer as a conductive path for plating. The method may include depositing a barrier layer on a substrate wherein the barrier layer provides adhesion for seed layer material and inhibits migration of the seed layer material, forming at least one isolated seed layer area on the barrier layer on the substrate, and depositing the metal material on the at least one isolated seed layer area using an electrochemical deposition process wherein the barrier layer provides a current path to deposit the metal material on the at least one isolated seed layer area.

A method of forming an integrated circuit structure includes forming an etch stop layer over a conductive feature, forming a dielectric layer over the etch stop layer, forming an opening in the dielectric layer to reveal the etch stop layer, and etching the etch stop layer through the opening using an etchant comprising an inhibitor. An inhibitor film comprising the inhibitor is formed on the conductive feature. The method further includes depositing a conductive barrier layer extending into the opening, performing a treatment to remove the inhibitor film after the conductive barrier layer is deposited, and depositing a conductive material to fill a remaining portion of the opening.

A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.

Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on a first metallic surface relative to a second surface comprising silicon. In some embodiments the reaction chamber in which the selective deposition occurs may optionally be passivated prior to carrying out the selective deposition process. In some embodiments selectivity of above about 50% or even about 90% is achieved.