In various embodiments a method for manufacturing a metallization layer on a substrate is provided, wherein the method may include providing a structured layer of a catalyst material on the substrate, the catalyst material may include a first layer of material arranged over the substrate and a second layer of material arranged over the first layer of material, wherein the structured layer of catalyst material having a first set of regions including the catalyst material over the substrate and a second set of regions free of the catalyst material over the substrate, and forming a plurality of groups of nanotubes over the substrate, each group of the plurality of groups of nanotubes includes a plurality of nanotubes formed over a respective region in the first set of regions.

The present disclosure describes a semiconductor device with a nitrided capping layer and methods for forming the same. One method includes forming a first conductive structure in a first dielectric layer on a substrate, depositing a second dielectric layer on the first conductive structure and the first dielectric layer, and forming an opening in the second dielectric layer to expose the first conductive structure and a portion of the first dielectric layer. The method further includes forming a nitrided layer on a top portion of the first conductive structure, a top portion of the portion of the first dielectric layer, sidewalls of the opening, and a top portion of the second dielectric layer, and forming a second conductive structure in the opening, where the second conductive structure is in contact with the nitrided layer.

Embodiments disclosed herein generally relate to methods of depositing a plurality of layers. A doped copper seed layer is deposited in a plurality of feature definitions in a device structure. A first copper seed layer is deposited and then the first copper seed layer is doped to form a doped copper seed layer, or a doped copper seed layer is deposited directly. The doped copper seed layer leads to increased flowability, reducing poor step coverage, overhang, and voids in the copper layer.

Wafers including a diamond layer and a semiconductor layer having III-Nitride compounds and methods for fabricating the wafers are provided. A nucleation layer, at least one semiconductor layer having III-Nitride compound and a protection layer are formed on a silicon substrate. Then, a silicon carrier wafer is glass bonded to the protection layer. Subsequently the silicon substrate, nucleation layer and a portion of the semiconductor layer are removed. Then, an intermediate layer, a seed layer and a first diamond layer are sequentially deposited on the III-Nitride layer. Next, the silicon carrier wafer and the protection layer are removed. Then, a silicon substrate wafer that includes a protection layer, silicon substrate and a diamond layer is prepared and glass bonded to the first diamond layer.

The present application discloses a method for fabricating a conductive layer stack. The method includes forming an intervening layer on an under-layer; and forming a filler layer on the intervening layer, wherein the filler layer comprises tungsten. The intervening layer comprises tungsten silicide and a thickness of the intervening layer is greater than 4.1 nm. The under-layer comprises titanium nitride and comprises a columnar grain structure.

The present application discloses a conductive layer stack, a semiconductor device and methods for fabricating the conductive layer stack and the semiconductor device. The conductive layer stack includes an intervening layer comprising tungsten silicide and positioned on an under-layer; a filler layer comprising tungsten and positioned on the intervening layer. The under-layer comprises titanium nitride and comprises a columnar grain structure. A thickness of the intervening layer is greater than about 4.1 nm.

Stacked die modules for semiconductor device assemblies and methods of manufacturing the modules are disclosed. In some embodiments, the module includes a shingled stack of semiconductor dies, each die having an uncovered porch with bond pads. Further, a dielectric structure partially encapsulates the shingled stack of semiconductor dies. The dielectric structure includes openings corresponding to the bond pads. The module also includes conductive structures disposed on the dielectric structure, where each of the conductive structures extends over at least one porch of the semiconductor dies to connect to at least one bond pad through a corresponding opening. The semiconductor device assembly may include a controller die attached to a package substrate, the controller die carrying one or more stacked die modules, and bonding wires connecting terminals of the modules to package bond pads.

An embodiment device includes: a first dielectric layer; a first photonic die and a second photonic die disposed adjacent a first side of the first dielectric layer; a waveguide optically coupling the first photonic die to the second photonic die, the waveguide being disposed between the first dielectric layer and the first photonic die, and between the first dielectric layer and the second photonic die; a first integrated circuit die and a second integrated circuit die disposed adjacent the first side of the first dielectric layer; conductive features extending through the first dielectric layer and along a second side of the first dielectric layer, the conductive features electrically coupling the first photonic die to the first integrated circuit die, the conductive features electrically coupling the second photonic die to the second integrated circuit die; and a second dielectric layer disposed adjacent the second side of the first dielectric layer.

Provided herein are methods and apparatuses for filling features metal-containing materials. One aspect of the disclosure relates to a method for filling structures with a metal-containing material, the method including: providing a structure to be filled with a metal-containing material, exposing the structure to multiple deposition cycles, with each deposition cycle including exposure to one or more alternating reducing agent (e.g. hydrogen (H2)) dose/inert gas purge pulses pulse followed by exposure to one or more alternating metal precursor dose pulses and inert gas purge pulses. The metal may be tungsten (W) or molybdenum (Mo) in some embodiments. In some embodiments, the structure is a partially fabricated (3-D) NAND structure. Apparatuses to perform the methods are also provided.

The disclosure provides a semiconductor structure and a method for manufacturing a semiconductor structure, relates to the field of semiconductor manufacturing technologies. The semiconductor structure includes: a substrate, having a bit line groove; a bit line, located in the bit line groove, and extending in a first direction; and a vertical transistor, located on the bit line. The bit line includes a bit line contact structure, and the bit line contact structure is a concave structure and/or a convex structure. The vertical transistor is electrically connected to the bit line by the bit line contact structure.