A metal-insulator-metal (MIM) capacitor module is provided. The MIM capacitor module includes a bottom electrode base formed in a lower metal layer, a bottom electrode conductively coupled to the bottom electrode base, a planar insulator formed over the bottom electrode, and a top electrode formed in an upper metal layer over the insulator. The bottom electrode includes a cup-shaped bottom electrode component and a bottom electrode fill component formed in an interior opening defined by the cup-shaped bottom electrode component.

The present disclosure relates to a method for preparing a semiconductor device with a composite landing pad. The method includes forming a first dielectric layer over a semiconductor substrate. The method also includes forming a barrier layer and a first lower metal plug penetrating through the first dielectric layer and in a cell region. The first lower metal plug is surrounded by the barrier layer. The method further includes depositing a silicon layer over the first dielectric layer, the barrier layer and the first lower metal plug. In addition, the method includes performing a salicide process to form an inner silicide portion over the first lower metal plug and an outer silicide portion over the barrier layer after the silicon layer is formed. The inner silicide portion is surrounded by the outer silicide portion, and a recess is formed over the inner silicide portion.

The present application discloses a method for fabricating a semiconductor device with a self-aligned landing pad. The method includes: providing a substrate; forming a dielectric layer with a plug over the substrate; performing an etching process to remove a portion of the dielectric layer to expose a protruding portion of the plug; forming a liner layer covering the dielectric layer and the protruding portion; and performing a thermal process to form a landing pad over the dielectric layer. The landing pad comprises a protruding portion of the plug, a first silicide layer disposed over the protruding portion, and a second silicide layer disposed on a sidewall of the protruding portion.

This disclosure relates to the technical field of semiconductor manufacturing, and discloses a semiconductor structure and a method for forming the same. The method includes: providing a semiconductor substrate having a plurality of contact structures arranged at an interval on a surface thereof, and the contact structures protruding from the substrate; forming a first dielectric layer on a side wall of the contact structure; depositing a second dielectric layer on surfaces of the semiconductor substrate, the contact structure and the first dielectric layer; enabling the first dielectric layer to react with the second dielectric layer; and removing an unreacted portion of the second dielectric layer by etching.

The present application discloses a method for fabricating a semiconductor device with a self-aligned landing pad. The method includes: providing a substrate; forming a dielectric layer with a plug over the substrate; performing an etching process to remove a portion of the dielectric layer to expose a protruding portion of the plug; forming a liner layer covering the dielectric layer and the protruding portion; and performing a thermal process to form a landing pad over the dielectric layer. The landing pad comprises a protruding portion of the plug, a first silicide layer disposed over the protruding portion, and a second silicide layer disposed on a sidewall of the protruding portion.

A planarization apparatus comprising a superstrate chuck is provided. The superstrate includes a plurality of inner lands protruding from a surface of the superstrate chuck and a peripheral land protruding from the surface of the superstrate chuck along a periphery of the superstrate chuck and encircling the inner lands therein. The peripheral land has a height smaller than a height of each of the inner lands. The peripheral land has a width sufficiently larger than a width of each of the inner lands such that a pressure leakage through the peripheral land is controlled to be less than a threshold.

Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.

Methods and Apparatuses for making an integrated circuit (IC) are disclosed. In accordance with some embodiments, a method including forming one or more decoupling capacitor (DCAP) cells comprising one or more polysilicon (PO) layers openings formed based on one or more photoresist layer openings formed to solve one or more design rule check (DRC) violations. The one or more DCAP cells also provide decoupling capacitors for the IC.

A semiconductor device includes: a plurality of lower electrodes arranged on a substrate in a first direction, which is parallel to a main surface of the substrate, and a second direction parallel to the main surface of the substrate and perpendicular to the first direction; and a support structure pattern configured to connect the plurality of lower electrodes to each other to support the plurality of lower electrodes, on the substrate and including a plurality of open portions. The plurality of open portions have shapes extending longer in the second direction than in the first direction, and when viewed from inner sides of the plurality of open portions, the plurality of open portions are convex in the first direction and are concave in the second direction.

In an integrated circuit, a metal-insulator-metal (MIM) diode includes: a first metallization structure level having a first metal layer; a first dielectric layer over the first metal layer; a metal contact or via on the first metal layer and extending through a portion of the first dielectric layer; and a second metallization structure level having a second metal layer; and a second dielectric layer over the second metal layer. The diode has a first electrode on the metal contact or via, a multilayer dielectric structure on the first electrode, and a second electrode between the multilayer dielectric structure and the second metal layer.