A method of forming a metal-insulator-metal (MIM) capacitor with copper top and bottom plates may begin with a copper interconnect layer (e.g., Cu MTOP) including a copper structure defining the capacitor bottom plate. A passivation region is formed over the bottom plate, and a wide top plate opening is etched in the passivation region, to expose the bottom plate. A dielectric layer is deposited into the top plate opening and onto the exposed bottom plate. Narrow via opening(s) are then etched in the passivation region. The wide top plate opening and narrow via opening(s) are concurrently filled with copper to define a copper top plate and copper via(s) in contact with the bottom plate. A first aluminum bond pad is formed on the copper top plate, and a second aluminum bond pad is formed in contact with the copper via(s) to provide a conductive coupling to the bottom plate.

A method of forming a metal-insulator-metal (MIM) capacitor with copper top and bottom plates may begin with a copper interconnect layer (e.g., Cu MTOP) including a copper structure defining the capacitor bottom plate. A passivation region is formed over the bottom plate, and a wide top plate opening is etched in the passivation region, to expose the bottom plate. A dielectric layer is deposited into the top plate opening and onto the exposed bottom plate. Narrow via opening(s) are then etched in the passivation region. The wide top plate opening and narrow via opening(s) are concurrently filled with copper to define a copper top plate and copper via(s) in contact with the bottom plate. A first aluminum bond pad is formed on the copper top plate, and a second aluminum bond pad is formed in contact with the copper via(s) to provide a conductive coupling to the bottom plate.

A metal-insulator-metal (MIM) capacitor module is provided. The MIM capacitor module includes a bottom electrode base formed in a lower metal layer, a bottom electrode conductively coupled to the bottom electrode base, a planar insulator formed over the bottom electrode, and a top electrode formed in an upper metal layer over the insulator. The bottom electrode includes a cup-shaped bottom electrode component and a bottom electrode fill component formed in an interior opening defined by the cup-shaped bottom electrode component.

An integrated circuit structure including a metal-insulator-metal (MIM) capacitor module and a thin-film resistor (TFR) module is provided. The MIM capacitor module includes a bottom electrode base formed in a lower metal layer, a bottom electrode formed in a dielectric region between the lower metal layer and an upper metal layer, an insulator formed over the bottom electrode, and a top electrode formed in the upper metal layer over the insulator. The bottom electrode includes a cup-shaped bottom electrode component and a bottom electrode fill component formed in an interior opening defined by the cup-shaped bottom electrode component. The TFR module includes a pair of metal heads formed in the dielectric region and a resistor element connected across the pair of metal heads. Each metal head includes a cup-shaped head component and a head fill component formed in an interior opening defined by the cup-shaped head component.

A system and method for fabricating on-die metal-insulator-metal capacitors capable of supporting relatively high voltage applications and increasing capacitance per area are described. In various implementations, an integrated circuit includes multiple metal-insulator-metal (MIM) capacitors. The MIM capacitors are formed between two signal nets such as two different power rails, two different control signals, or two different data signals. The integrated circuit includes multiple intermediate metal layers (or metal plates) formed between two signal nets. In high voltage regions, a MIM capacitor has one or more intermediate metal plates formed as floating plates between electrode metal plates. The floating plates have no connection to any power supply reference voltage level used by the integrated circuit. The insulating distance between the two electrode metal plates includes the thicknesses of the two dielectric layers, but the thickness of the conductive floating metal plate does not contribute to this insulating distance.

A semiconductor device and a manufacturing method for the same are provided in such a manner that the oxygen barrier film and the conductive plug in the base of a capacitor are prevented from being abnormally oxidized. A capacitor is formed by layering a lower electrode, a dielectric film including a ferroelectric substance or a high dielectric substance, and an upper electrode in this order on top of an interlayer insulation film with at least a conductive oxygen barrier film in between, and at least a portion of a side of the conductive oxygen barrier film is covered with an oxygen entering portion or an insulating oxygen barrier film.

Described herein are ferroelectric (FE) memory cells that include transistors having gate stacks separate from FE capacitors of these cells. An example memory cell may be implemented as an IC device that includes a support structure (e.g., a substrate) and a transistor provided over the support structure and including a gate stack. The IC device also includes a FE capacitor having a first capacitor electrode, a second capacitor electrode, and a capacitor insulator of a FE material between the first capacitor electrode and the second capacitor electrode, where the FE capacitor is separate from the gate stack (i.e., is not integrated within the gate stack and does not have any layers that are part of the gate stack). The IC device further includes an interconnect structure, configured to electrically couple the gate stack and the first capacitor electrode.

A method for manufacturing a capacitor includes: forming a polysilicon layer on a substrate; forming a polysilicon structure by etching the polysilicon layer, wherein the polysilicon structure comprises a lower electrode plate of the capacitor; forming sidewalls on two sides of the polysilicon structure; depositing a dielectric layer and a conductive layer sequentially; performing a photolithography process to define salicide block layer patterns and upper electrode plate patterns of the capacitor; forming a salicide block layer, and an upper electrode plate and a dielectric layer of the capacitor, by sequentially etching the conductive layer and the dielectric layer, according to the salicide block layer patterns and the upper electrode plate patterns of the capacitor; and forming salicides.

A metal-insulator-metal (MIM) capacitor module includes an outer electrode, an insulator, an inner electrode, an outer electrode extension structure, an inner electrode contact element, and an outer electrode contact element. The outer electrode includes a plurality of vertically-extending outer electrode sidewalls. The insulator is formed in an opening defined by the vertically-extending outer electrode sidewalls, and includes a plurality of vertically-extending insulator sidewalls. The inner electrode formed in an interior opening defined by the insulator. The outer electrode extension structure extends laterally from a particular vertically-extending outer electrode sidewall. The inner electrode contact element and outer electrode contact element are formed in a metal layer. The inner electrode contact element is electrically connected to the inner electrode, and the outer electrode contact element is electrically connected to the outer electrode extension structure.

A method of forming a metal-insulator-metal (MIM) capacitor with copper top and bottom plates may begin with a copper interconnect layer (e.g., Cu MTOP) including a copper structure defining the capacitor bottom plate. A passivation region is formed over the bottom plate, and a wide top plate opening is etched in the passivation region, to expose the bottom plate. A dielectric layer is deposited into the top plate opening and onto the exposed bottom plate. Narrow via opening(s) are then etched in the passivation region. The wide top plate opening and narrow via opening(s) are concurrently filled with copper to define a copper top plate and copper via(s) in contact with the bottom plate. A first aluminum bond pad is formed on the copper top plate, and a second aluminum bond pad is formed in contact with the copper via(s) to provide a conductive coupling to the bottom plate.