H01L21/8206

Doped Diamond SemiConductor and Method of Manufacture
20180301535 · 2018-10-18 ·

A doped diamond semiconductor and method of production using a laser is disclosed herein. As disclosed, a dopant and/or a diamond or sapphire seed material may be added to a graphite based ablative layer positioned below a confinement layer, the ablative layer also being graphite based and positioned above a backing layer, to promote formation of diamond particles having desirable semiconductor properties via the action of a laser beam upon the ablative layer. Dopants may be incorporated into the process to activate the reaction sought to produce a material useful in production of a doped semiconductor or a doped conductor suitable for the purpose of modulating the electrical, thermal or quantum properties of the material produced. As disclosed, the diamond particles formed by either the machine or method of confined pulsed laser deposition disclosed may be arranged as semiconductors, electrical components, thermal components, quantum components and/or integrated circuits.

Doped Diamond SemiConductor and Method of Manufacture
20180114835 · 2018-04-26 ·

A doped diamond semiconductor and method of production using a laser is disclosed herein. As disclosed, a dopant and/or a diamond or sapphire seed material may be added to a graphite based ablative layer positioned below a confinement layer, the ablative layer also being graphite based and positioned above a backing layer, to promote formation of diamond particles having desirable semiconductor properties via the action of a laser beam upon the ablative layer. Dopants may be incorporated into the process to activate the reaction sought to produce a material useful in production of a doped semiconductor or a doped conductor suitable for the purpose of modulating the electrical, thermal or quantum properties of the material produced. As disclosed, the diamond particles formed by either the machine or method of confined pulsed laser deposition disclosed may be arranged as semiconductors, electrical components, thermal components, quantum components and/or integrated circuits.

Compact CMOS
12136661 · 2024-11-05 ·

A Compact CMOS System having a non-split Channel Regions Controlling Gate, including a material which forms rectifying junctions with both N and P-type Field Induced Semiconductor, and at least two Channels electrically connected thereto and projecting substantially away therefrom adjacent and parallel to one another. There further being substantially non-rectifying junctions to the material which forms a rectifying junction with both N and P-type Field Induced Semiconductor, and to distal ends of the at least two Channels.

Doped Diamond Semi-Conductor and Method of Manufacture
20180006121 · 2018-01-04 ·

A doped diamond semiconductor and method of production using a laser is disclosed herein. As disclosed, a dopant and/or a diamond or sapphire seed material may be added to a graphite based ablative layer positioned below a confinement layer, the ablative layer also being graphite based and positioned above a backing layer, to promote formation of diamond particles having desirable semiconductor properties via the action of a laser beam upon the ablative layer. As disclosed, the diamond particles formed by either the machine or method of confined pulsed laser deposition disclosed may be arranged as semiconductors, electrical components, thermal components, quantum components and/or integrated circuits.

VERTICAL JUNCTION FIELD-EFFECT TRANSISTORS WITH SOURCE-DRAIN DIODE CELLS INTEGRATED AT DIE LEVEL
20240421151 · 2024-12-19 ·

This disclosure relates to a semiconductor die and a method for fabrication of a semiconductor die. The disclosed semiconductor die comprises a substrate having a drain-cathode region, a plurality of trenches and mesas, a first anode trench, and a first floating closed loop mesa surrounding the first anode trench. The semiconductor die further comprises a first anode region under the first anode trench, a plurality of source regions extending from top surfaces into the plurality of mesas, and a plurality of gate regions extending along a bottom surface and portions of sidewalls of each of the plurality of trenches. The first floating closed loop mesa electrically isolates the first anode region from the plurality of gate regions, and the first anode region electrically couples to the plurality of source regions to integrate an anti-parallel diode cell within vertical junction field-effect transistors (JFETs).