An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS thin-film transistors (TFT).

Provided are a superlattice structure including a two-dimensional material and a device including the superlattice structure. The superlattice structure may include at least two different two-dimensional (2D) materials bonded to each other in a lateral direction, and an interfacial region of the at least two 2D materials may be strained. The superlattice structure may have a bandgap adjusted by the interfacial region that is strained. The at least two 2D materials may include first and second 2D materials. The first 2D material may have a first bandgap in an intrinsic state thereof. The second 2D material may have a second bandgap in an intrinsic state thereof. An interfacial region of the first and second 2D materials and an adjacent region may have a third bandgap between the first bandgap and the second bandgap.

A memory cell is disclosed. The memory cell includes a transistor and a capacitor. The transistor includes a source region, a drain region, and a channel region including an indium gallium zinc oxide (IGZO, which is also known in the art as GIZO) material. The capacitor is in operative communication with the transistor, and the capacitor includes a top capacitor electrode and a bottom capacitor electrode. Also disclosed is a semiconductor device including a dynamic random access memory (DRAM) array of DRAM cells. Also disclosed is a system including a memory array of DRAM cells and methods for forming the disclosed memory cells and arrays of cells.

A memory cell is disclosed. The memory cell includes a transistor and a capacitor. The transistor includes a source region, a drain region, and a channel region including an indium gallium zinc oxide (IGZO, which is also known in the art as GIZO) material. The capacitor is in operative communication with the transistor, and the capacitor includes a top capacitor electrode and a bottom capacitor electrode. Also disclosed is a semiconductor device including a dynamic random access memory (DRAM) array of DRAM cells. Also disclosed is a system including a memory array of DRAM cells and methods for forming the disclosed memory cells and arrays of cells.

A memory cell is disclosed. The memory cell includes a transistor and a capacitor. The transistor includes a source region, a drain region, and a channel region including an indium gallium zinc oxide (IGZO, which is also known in the art as GIZO) material. The capacitor is in operative communication with the transistor, and the capacitor includes a top capacitor electrode and a bottom capacitor electrode. Also disclosed is a semiconductor device including a dynamic random access memory (DRAM) array of DRAM cells. Also disclosed is a system including a memory array of DRAM cells and methods for forming the disclosed memory cells and arrays of cells.

A memory cell is disclosed. The memory cell includes a transistor and a capacitor. The transistor includes a source region, a drain region, and a channel region including an indium gallium zinc oxide (IGZO, which is also known in the art as GIZO) material. The capacitor is in operative communication with the transistor, and the capacitor includes a top capacitor electrode and a bottom capacitor electrode. Also disclosed is a semiconductor device including a dynamic random access memory (DRAM) array of DRAM cells. Also disclosed is a system including a memory array of DRAM cells and methods for forming the disclosed memory cells and arrays of cells.

In some embodiments, a method of processing a substrate disposed atop a substrate support in a physical vapor deposition process chamber includes: (a) forming a plasma from a process gas within a processing region of the physical vapor deposition chamber, wherein the process gas comprises an inert gas to sputter silicon from a surface of a target within the processing region of the physical vapor deposition chamber; and (b) depositing an amorphous silicon layer atop a first layer on the substrate, wherein the first layer comprises one or more metal oxides of indium (In), gallium (Ga), zinc (Zn), tin (Sn) or combinations thereof.

In some embodiments, a method of processing a substrate disposed atop a substrate support in a physical vapor deposition process chamber includes: (a) forming a plasma from a process gas within a processing region of the physical vapor deposition chamber, wherein the process gas comprises an inert gas to sputter silicon from a surface of a target within the processing region of the physical vapor deposition chamber; and (b) depositing an amorphous silicon layer atop a first layer on the substrate, wherein the first layer comprises one or more metal oxides of indium (In), gallium (Ga), zinc (Zn), tin (Sn) or combinations thereof.

Some embodiments include an integrated assembly having an active region which contains semiconductor material. The active region includes first, second and third source/drain regions within the semiconductor material, includes a first channel region within the semiconductor material and between the first and second source/drain regions, and includes a second channel region within the semiconductor material and between the second and third source/drain regions. The semiconductor material includes at least one element selected from Group 13 of the periodic table. A digit line is electrically coupled with the second source/drain region. A first transistor gate is operatively proximate the first channel region. A second transistor gate is operatively proximate the second channel region. A first storage-element is electrically coupled with the first source/drain region. A second storage-element is electrically coupled with the third source/drain region. Some embodiments include methods of forming integrated assemblies.

An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS thin-film transistors (TFT).