Methods and systems disclosed herein can measure thin film stacks, such as film on grating and bandgap on grating in semiconductors. For example, the thin film stack may be a 1D film stack, a 2D film on grating, or a 3D film on grating. One or more effective medium dispersion models are created for the film stack. Each effective medium dispersion model can substitute for one or more layers. A thickness of one or more layers can be determined using the effective medium dispersion based scatterometry model. In an instance, three effective medium dispersion based scatterometry models are developed and used to determine thickness of three layers in a film stack.

A gettering property evaluation apparatus includes a gettering determination unit and a chuck table. The gettering determination unit has a laser beam applying unit for applying a laser beam to a wafer, and a transmission-reception unit for applying a microwave to the wafer and receiving the microwave reflected by the wafer. The gettering determination unit determines whether or not a gettering layer including a grinding strain generated by grinding the wafer has a gettering property. The chuck table holds the wafer on a holding surface. The chuck table has a conductive nonmetallic porous member constituting the holding surface and having a property of reflecting or absorbing the microwave, and a base member provided with a negative pressure transmission passage for transmitting a negative pressure to the nonmetallic porous member.

Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate and the components are connected with conductive material in preformed holes in dielectric material in the bond lines aligned with TSVs of the devices and the exposed conductors of the substrate. Methods of fabrication are also disclosed.

To facilitate evaluation of a predicted process shape in process recipe development using machine learning, a process recipe search apparatus that searches for an etching recipe that is a parameter of a plasma processing apparatus set so as to etch a sample into a desired shape displays, on a display device, the predicted process shape of the sample by a candidate etching recipe predicted by using a machine leaning model, by highlighting a difference between the predicted process shape and a target shape.

There is provided a film thickness measurement method which measures a film thickness of a specific film to be measured in a multilayer film in situ in a film formation system that forms the multilayer film on a substrate, the method comprising: regarding a plurality of films located under the film to be measured as one underlayer film, measuring a film thickness of the underlayer film, and deriving an optical constant of the underlayer film by spectroscopic interferometry; and after the film to be measured is formed, deriving a film thickness of the film to be measured by spectroscopic interferometry using the film thickness and the optical constant of the underlayer film.

An ink jet process is used to deposit a material layer to a desired thickness. Layout data is converted to per-cell grayscale values, each representing ink volume to be locally delivered. The grayscale values are used to generate a halftone pattern to deliver variable ink volume (and thickness) to the substrate. The halftoning provides for a relatively continuous layer (e.g., without unintended gaps or holes) while providing for variable volume and, thus, contributes to variable ink/material buildup to achieve desired thickness. The ink is jetted as liquid or aerosol that suspends material used to form the material layer, for example, an organic material used to form an encapsulation layer for a flat panel device. The deposited layer is then cured or otherwise finished to complete the process.

Systems and methods disclosed are generally related to masklessly developing connections between a chip-group and a design connection point on a substrate. In placement of the chip-group on the substrate, according to certain embodiments the chip-group may be dispositioned relative to an expected position per a substrate layout design, causing a connection misalignment with the design connection point. According to certain embodiments, a machine learning (ML) model is trained on historical and simulated pixel models of chip-group connections and design connection points. Upon determining the chip-group misalignment by a metrology measurement, the trained ML model determines a pixel model to connect the misaligned chip-group, and causes the pixel model to be exposed to a substrate with a digital lithography tool, thereby connecting the dispositioned chip-group to the design connection point.

A method of controlling gate formation of a semiconductor device includes acquiring a correlation between gate critical dimensions (CDs) and etching recipes for forming gate trenches; measuring a gate CD on a target wafer; determining an etching recipe based on the correction and the measured gate CD; and performing an etching process on the target wafer to form a gate trench with the determined etching recipe.

The invention is directed to a method for the production of an optoelectronic module including a support (5) and an additional layer, said support being formed by an assembly (25) which has no optoelectronic properties and which comprises, successively, a metal substrate (27), a dielectric coating (29) disposed on the metal substrate, and an electrically conductive layer (31) disposed on the dielectric coating. The production method comprises: a step of providing the support and performing a method in which the support is checked, or providing the support after it has already been checked; and a step of depositing at least one additional layer on the electrically conductive layer. The method in which support is checked comprises the following steps: electrical excitation of the support by bringing the metal substrate and the electrically conductive layer into electrical contact with a voltage source (33); and photothermal examination of the excited support so as to detect any possible fault (49, 51) located at least partially in the dielectric coating (29) and to provide a photothermal examination result.

A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating layer and conductive layer formed over the insulating layer. A vertical interconnect structure and semiconductor die are disposed over the first build-up interconnect structure. The semiconductor die, first build-up interconnect structure, and substrate are disposed over a carrier. An encapsulant is deposited over the semiconductor die, first build-up interconnect structure, and substrate. A second build-up interconnect structure is formed over the encapsulant. The second build-up interconnect structure electrically connects to the first build-up interconnect structure through the vertical interconnect structure. The substrate provides structural support and prevents warpage during formation of the first and second build-up interconnect structures. The substrate is removed after forming the second build-up interconnect structure. A portion of the insulating layer is removed exposing the conductive layer for electrical interconnect with subsequently stacked semiconductor devices.