H01L22/12

SYSTEMS AND METHODS FOR PROCESSING SEMICONDUCTOR WAFERS USING FRONT-END PROCESSED WAFER GLOBAL GEOMETRY METRICS
20230050442 · 2023-02-16 ·

A method for processing semiconductor wafers includes obtaining measurement data from a surface of a semiconductor wafer processed by a front-end process tool. The method includes determining a center plane of the wafer based on the measurement data, generating raw shape profiles, and generating ideal shape profiles. The method further includes generating Gapi profiles based on the raw shape profiles and the ideal shape profiles, and calculating a Gapi value of the semiconductor wafer based on the Gapi profiles. The generated Gapi profiles and/or the calculated Gapi value may be used to tune the front-end process tool and/or sort the semiconductor wafer for polishing. Systems include at least a front-end process tool, a flatness measurement tool, and a computing device.

DISPLAY SUBSTRATE, DISPLAY DEVICE, AND DETECTION METHOD FOR DISPLAY SUBSTRATE

The embodiments of the present disclosure provide a display substrate, a display device, and a detection method for the display substrate. The display substrate includes: a base substrate including a display region and a peripheral region located on at least one side of the display region; a crack stopper located in the peripheral region and configured to prevent a crack from propagating toward the display region; an encapsulation structure disposed on the base substrate and covering the display region; and a crack detection structure disposed on the base substrate, wherein the crack detection structure is located on a side of the crack stopper facing the display region, an orthographic projection of the crack detection structure on the base substrate falls within an orthographic projection of the encapsulation structure on the base substrate, and the crack detection structure is configured to detect whether a crack exists in the encapsulation structure.

SYSTEMS AND METHODS FOR PROCESSING SEMICONDUCTOR WAFERS USING FRONT-END PROCESSED WAFER EDGE GEOMETRY METRICS

A method for processing semiconductor wafers includes obtaining measurement data of an edge profile of a semiconductor wafer processed by a front-end process tool. The method includes determining an edge profile center point based on the measurement data, generating a raw height profile, and generating an ideal edge profile. The method further includes generating a Gapi edge profile of the semiconductor wafer based on the raw height profile and the ideal edge profile and calculating a Gapi edge value of the semiconductor wafer based on the Gapi edge profile. The generated Gapi edge profile and/or the calculated Gapi edge value may be used to tune the front-end process tool and/or sort the semiconductor wafer for polishing. Systems include at least a front-end process tool, a flatness measurement tool, and a computing device.

MEMORY DEVICE FOR WAFER-ON-WAFER FORMED MEMORY AND LOGIC

A memory device includes an array of memory cells configured on a die or chip and coupled to sense lines and access lines of the die or chip and a respective sense amplifier configured on the die or chip coupled to each of the sense lines. Each of a plurality of subsets of the sense lines is coupled to a respective local input/output (I/O) line on the die or chip for communication of data on the die or chip and a respective transceiver associated with the respective local I/O line, the respective transceiver configured to enable communication of the data to one or more device off the die or chip.

SYSTEMS AND METHODS FOR DETERMINING FLOW CHARACTERISTICS OF A FLUID SEGMENT FOR ANALYTIC DETERMINATIONS
20230050586 · 2023-02-16 ·

Systems and methods are described for determining whether liquid remains on a wafer surface following a scanning operation. A system embodiment includes, but is not limited to, a first system configured for positioning adjacent a transfer line coupled with a scanning nozzle to dispense fluid onto a wafer surface and to recover the fluid from the wafer surface, the first system configured to detect a gas/liquid transition of the fluid and determine a volume of liquid sample dispensed; a second system configured for positioning adjacent a second line downstream from the scanning nozzle, the second system configured to detect a gas/liquid transition of fluid flowing through the second line and determine a volume of liquid sample recovered from the wafer surface; and a controller configured to generate an alert if the volume of liquid sample recovered is not within a threshold amount compared to the volume of liquid sample dispensed.

ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME

A method for manufacturing an electronic device is provided, the method includes: providing an inspection module to inspect a first area of the electronic device to obtain a first information and inspect a second area of the electronic device to obtain a second information; transmitting the first information and the second information to a processing system; comparing the first information and the second information to obtain a difference; and transmitting a correction information to a first process machine via a first interface system. When the difference is greater than or equal to -2 and less than or equal to 2, the first process machine is started to produce. An electronic device is also provided.

ELECTRONIC DEVICE AND MANUFACTURING METHOD AND INSPECTION METHOD THEREOF

An electronic device is disclosed and includes a conductive layer, a first dielectric layer, and a second dielectric layer, in which the second dielectric layer is disposed on the first dielectric layer, the conductive layer is disposed between the first dielectric layer and the second dielectric layer, the first dielectric layer has a first transmittance for a light, the second dielectric layer has a second transmittance for the light, and the first transmittance is different from the second transmittance.

UNIT SPECIFIC VARIABLE OR ADAPTIVE METAL FILL AND SYSTEM AND METHOD FOR THE SAME
20230047504 · 2023-02-16 ·

A method of forming a semiconductor device can comprise providing a first shift region in which to determine a first displacement. A second shift region may be provided in which to determine a second displacement. A unique electrically conductive structure may be formed comprising traces to account for the first displacement and the second displacement. The electrically conductive structure may comprise traces comprising a first portion within the first shift region and a second portion of traces in the second shift region laterally offset from the first portion of traces. A third portion of the traces may be provided in the routing area between the first shift region and the second shift region. A unique variable metal fill may be formed within the fill area. The variable metal fill may be electrically isolated from the unique electrically conductive structure.

DEFECT INSPECTION SYSTEM AND METHOD OF USING THE SAME

A method includes patterning a hard mask over a target layer, capturing a low resolution image of the hard mask, and enhancing the low resolution image of the hard mask with a first machine learning model to produce an enhanced image of the hard mask. The method further includes analyzing the enhanced image of the hard mask with a second machine learning model to determine whether the target layer has defects.

Semiconductor device including paired marks and method for manufacturing semiconductor device
11581265 · 2023-02-14 · ·

A semiconductor device of an embodiment includes a plurality of chip regions, each including a memory region in which a plurality of memory cells is arranged, and a kerf region disposed between the chip regions and surrounding each chip region. Paired marks are arranged in a vicinity of the memory region of one of the plurality of chip regions and in a common hierarchical layer in the kerf region, and the paired marks are disposed over upper and lower hierarchical layers.