The present invention provides a sensor mounted wafer, including: a lower case in which a mounting groove is formed; a circuit board on which a plurality of electronic components having different heights are mounted, and placed in the mounting groove; an upper case in which a plurality of insertion grooves having different depths are formed, and bonded together to the lower case so that the plurality of electronic components are inserted into the plurality of insertion grooves; and an adhesive layer placed between the mounting groove and the plurality of insertion grooves, in which the insertion grooves are formed to have different depths according to the heights of the plurality of the electronic components.

The embodiments of the present disclosure provide a semiconductor base plate and a test method thereof. When a first test line and a second test line in the semiconductor base plate are tested, a resistivity of the first test line can be tested by directly loading voltages to a first test pad and a second test pad after a first conductive layer is formed and before a first insulating layer is formed. After a second conductive layer is formed, a resistivity of the second test line is tested by loading voltages to a third test pad and a fourth test pad.

A method of characterizing a wide-bandgap semiconductor material is provided. A substrate is provided, which includes a layer stack of a conductive material layer, a dielectric material layer, and a wide-bandgap semiconductor material layer. A mercury probe is disposed on a top surface of the wide-bandgap semiconductor material layer. Alternating-current (AC) capacitance of the layer stack is determined as a function of a variable direct-current (DC) bias voltage across the conductive material layer and the wide-bandgap semiconductor material layer. A material property of the wide-bandgap semiconductor material layer is extracted from a profile of the AC capacitance as a function of the DC bias voltage.

A semiconductor structure includes: a semiconductor substrate; a first metal layer located on a surface of the semiconductor substrate; a second metal layer located above a surface of the first metal layer; an insulating layer located between the first metal layer and the second metal layer and configured to isolate the first metal layer from the second metal layer; and at least four vias located in the insulating layer and a conductive material for connecting the first metal layer and the second metal layer is filled in the at least four vias.

A method of determining a bonding status between a wire and at least one bonding location of a workpiece is provided. The method includes the steps of: (a) bonding a portion of a wire to a bonding location of a workpiece using a bonding tool of a wire bonding machine; (b) determining a motion profile of the bonding tool for determining if the portion of the wire is bonded to the bonding location, the motion profile being configured to result in the wire being broken during the motion profile if the portion of the wire is not bonded to the bonding location; and (c) moving the bonding tool along the motion profile to determine if the portion of the wire is bonded to the bonding location. Other methods of determining a bonding status between a wire and at least one bonding location of a workpiece are also provided.

The present application provides a method for verification of conductivity type of a silicon wafer. The method comprises measuring the resistivity of the silicon wafer to obtain a first resistivity, placing the silicon wafer under atmosphere of air for a predicted time period, measuring the resistivity of the silicon wafer to obtain a second resistivity, and determining conductivity type of the silicon wafer by comparing the first resistivity and the second resistivity. The method can be applied to a silicon wafer having a high resistivity such as higher than 500 ohm.sup.-cm to rapidly and accurately determine conductivity type of the silicon wafer. Advantages of the method of the present application include accurate test results, easy operation, simple device requirement, and reduced cost.

The invention provides a measuring method of resistivity of a wafer, comprising: choosing a wafer to be measured, conducting a thermal treatment for the wafer to remove a thermal doner in the wafer, conducting an oxidation process for the wafer to form an oxidized surface on the wafer, and measuring resistivity of the wafer. In the method, firstly, the wafer is oxidized to get the oxidized surface, so as to restrict surface variation when placing the wafer in a later process. Therefore, the resistivity measurement of the wafer surface only slightly varies.

The present disclosure relates to a latch-up test structure, including: a substrate of a first conductive type; a first well region of a second conductive type, located in the substrate of the first conductive type; a first doped region of the first conductive type, located in the first well region of the second conductive type; a first doped region of the second conductive type, located in the first well region of the second conductive type; and a second doped region of the first conductive type, a second doped region of the second conductive type, a third doped region of the first conductive type, and a third doped region of the second conductive type that are arranged at intervals in the substrate of the first conductive type.

In an embodiment, a method includes attaching a first package component to a first carrier, the first package component comprising: an aluminum pad disposed adjacent to a substrate; a sacrificial pad disposed adjacent to the substrate, the sacrificial pad comprising a major surface opposite the substrate, a protrusion of the sacrificial pad extending from the major surface; and a dielectric bond layer disposed around the aluminum pad and the sacrificial pad; attaching a second carrier to the first package component and the first carrier, the first package component being interposed between the first carrier and the second carrier; removing the first carrier; planarizing the dielectric bond layer to comprise a top surface being coplanar with the protrusion; and etching a portion of the protrusion.

A method of forming a semiconductor package includes attaching a first package component to a first carrier; attaching a second package component to the first carrier, the second package component laterally displaced from the first package component; attaching a third package component to the first package component, the third package component being electrically connected to the first package component; removing the first carrier from the first package component and the second package component; after removing the first carrier, performing a first circuit probe test on the second package component to obtain first test data of the second package component; and comparing the first test data of the second package component with prior data of the second package component.