H01L22/22

HIGH PIXEL DENSITY STRUCTURES AND METHODS OF MAKING

Methods of making high-pixel-density LED structures are described. The methods may include forming a backplane substrate and a LED substrate. The backplane substrate and the LED substrate may be bonded together, and the bonded substrates may include an array of LED pixels. Each of the LED pixels may include a group of isolated subpixels. A quantum dot layer may be formed on at least one of the isolated subpixels in each of the LED pixels. The methods may further include repairing at least one defective LED pixel by forming a replacement quantum dot layer on a quantum-dot-layer-free subpixel in the defective LED pixel. The methods may also include forming a UV barrier layer on the array of LED pixels after the repairing of the at least one defective LED pixel.

DISPLAY PANEL AND METHOD OF MANUFACTURING SAME
20220367770 · 2022-11-17 ·

A display panel of micro LEDs which provides a means of testing the installed micro LEDs for illumination qualities before final connections are made includes a transparent substrate, a plurality of electrode blocks on the transparent substrate, a plurality of conductive bonding blocks, and the micro LEDs. Each electrode block includes a slit allowing light to pass through. Each bonding block is on a surface of one electrode block away from the transparent substrate and is partially embedded in the slit of one corresponding electrode block. Each micro LED is fixed on one electrode block by a corresponding bonding block and is electrically connected with the electrode block. A method of manufacturing the display panel is further provided.

SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE
20220367642 · 2022-11-17 · ·

A type, size, and location of a crystal defect of an epitaxial layer of a semiconductor wafer containing silicon carbide are detected from a PL image by crystal defect inspection equipment. Detected crystal defects include a triangular polymorph stacking fault generated in the epitaxial layer during epitaxial growth and high-density BPDs extending from the stacking fault and present bundled between the stacking fault and a perfect crystal. Next, a chip region free of the triangular polymorph stacking fault and free of the high-density BPD in a specified area that is in the termination region and is located closer to a chip center than is a specified position is identified as a conforming product. A semiconductor chip set as a conforming product may contain high-density BPDs outside the specified area.

Pixel structure

A pixel structure including a substrate, a first conductor, a second conductor, and a plurality of dies is provided. The first conductor is disposed on the substrate and includes a plurality of first body portions extending along a first direction, a plurality of first branch portions extending along a second direction, and a plurality of second branch portions extending along the first direction. The second conductor is disposed on the substrate and includes a plurality of second body portions extending along the second direction and a plurality of third branch portions extending along the first direction. The die includes two electrodes, wherein the first branch portions are connected between the first body portions and the second branch portions, and the two electrodes are respectively connected to the first branch portions and the second body portions or respectively connected to the second branch portions and the third branch portions.

Less-secure processors, integrated circuits, wireless communications apparatus, methods for operation thereof, and methods for manufacturing thereof

An integrated circuit (122) includes an on-chip boot ROM (132) holding boot code, a non-volatile security identification element (140) having non-volatile information determining a less secure type or more secure type, and a processor (130). The processor (130) is coupled to the on-chip boot ROM (132) and to the non-volatile security identification element (140) to selectively execute boot code depending on the non-volatile information of the non-volatile security identification element (140). Other technology such as processors, methods of operation, processes of manufacture, wireless communications apparatus, and wireless handsets are also disclosed.

REPAIRING METHOD FOR MICRO-LED CHIP DEFECTIVE PIXELS
20230036183 · 2023-02-02 ·

A repairing method for micro-LED chip defective pixels is disclosed. By providing a main recess and a backup recess in each of sub-pixel areas of a substrate, wherein each of the main recesses is loaded with a main micro-LED chip, when all of the main micro-LED chips are detected for defective pixels, the backup recess in each of the sub-pixel areas where the defective pixel is detected is loaded with a backup micro-LED chip using a fluid mass transfer method, which improves the repair efficiency.

Tandem Micro-Light Emitting Diode Redundancy Architecture

A display system of a display includes multiple primary light emitting diodes and multiple secondary light emitting diodes. The multiple primary light emitting diodes may emit light, in which at least a first primary light emitting diode of the multiple primary light emitting diodes is shorted. Moreover, the multiple secondary light emitting diodes may emit light. At least a first secondary light emitting diode of the multiple secondary light emitting diodes is associated with the first primary light emitting diode, and the first secondary light emitting diode may emit light based at least in part on the first primary light emitting diode being shorted.

STACKED SEMICONDUCTOR DEVICE TEST CIRCUITS AND METHODS OF USE
20220344223 · 2022-10-27 ·

A control circuit is included in a first die of a stacked semiconductor device. The first die further includes a transistor that is electrically connected to the control circuit. The transistor is configured to be controlled by the control circuit to selectively block a die-to-die interconnect. In this way, the die-to-die interconnect may be selectively blocked to isolate the first die and a second die of the stacked semiconductor device for independent testing after bonding. This may increase the effectiveness of a testing to identify and isolate defects in the first die or the second die, which may further increase the effectiveness of performing rework or repair on the stacked semiconductor device.

LESS-SECURE PROCESSORS, INTEGRATED CIRCUITS, WIRELESS COMMUNICATIONS APPARATUS, METHODS FOR OPERATION THEREOF, AND METHODS FOR MANUFACTURING THEREOF

An integrated circuit (122) includes an on-chip boot ROM (132) holding boot code, a non-volatile security identification element (140) having non-volatile information determining a less secure type or more secure type, and a processor (130). The processor (130) is coupled to the on-chip boot ROM (132) and to the non-volatile security identification element (140) to selectively execute boot code depending on the non-volatile information of the non-volatile security identification element (140). Other technology such as processors, methods of operation, processes of manufacture, wireless communications apparatus, and wireless handsets are also disclosed.

Correction die for wafer/die stack
11605614 · 2023-03-14 · ·

Representative implementations of devices and techniques provide correction for a defective die in a wafer-to-wafer stack or a die stack. A correction die is coupled to a die of the stack with the defective die. The correction die electrically replaces the defective die. Optionally, a dummy die can be coupled to other die stacks of a wafer-to-wafer stack to adjust a height of the stacks.