The present disclosure describes a structure that includes a substrate with first and second sides, a device layer disposed on the first side of the substrate, having a fault detection area on a back-side surface of the device layer configured to emit a signal that is indicative of a presence or an absence of a defect in the device layer, a first interconnect structure disposed on a front-side of the device layer, and a second interconnect structure disposed on the second side of the substrate, having a metal-free region aligned with the fault detection area and a first metal layer having first and second conductive lines disposed substantially parallel to each other. First and second sidewalls of the first and second conductive lines, respectively, facing each other are substantially aligned with first and second sides of the fault detection area.

An integrated circuit includes first to n.sup.th metal layers vertically stacked on a substrate, and a test circuit outputting a test result signal according to a characteristic of each of the first to n.sup.th metal layers. The test circuit includes first to n.sup.th test circuits for generating a plurality of clock signals. Each clock signal of the plurality of clock signal has a frequency according to a characteristic of a corresponding metal layer among the first to n.sup.th metal layers, and n is a natural number.

The present invention provides a sensor mounted wafer, including: a lower case in which a mounting groove is formed; a circuit board on which a plurality of electronic components having different heights are mounted, and placed in the mounting groove; an upper case in which a plurality of insertion grooves having different depths are formed, and bonded together to the lower case so that the plurality of electronic components are inserted into the plurality of insertion grooves; and an adhesive layer placed between the mounting groove and the plurality of insertion grooves, in which the insertion grooves are formed to have different depths according to the heights of the plurality of the electronic components.

The embodiments of the present disclosure provide a display substrate, a display device, and a detection method for the display substrate. The display substrate includes: a base substrate including a display region and a peripheral region located on at least one side of the display region; a crack stopper located in the peripheral region and configured to prevent a crack from propagating toward the display region; an encapsulation structure disposed on the base substrate and covering the display region; and a crack detection structure disposed on the base substrate, wherein the crack detection structure is located on a side of the crack stopper facing the display region, an orthographic projection of the crack detection structure on the base substrate falls within an orthographic projection of the encapsulation structure on the base substrate, and the crack detection structure is configured to detect whether a crack exists in the encapsulation structure.

Damage to a joint part of a terminal of an electronic component mounted on a substrate is detected. The substrate includes a base material unit, a land, and a light detection unit. The land included in the substrate is arranged with a stress light emitting body configured to emit light in accordance with stress, includes a transparent member, and is joined with a terminal of an element arranged in the base material unit included in the substrate. The light detection unit included in the substrate is arranged between the base material unit and the land included in the substrate, and detects light from the stress light emitting body.

The embodiments of the present disclosure provide a semiconductor base plate and a test method thereof. When a first test line and a second test line in the semiconductor base plate are tested, a resistivity of the first test line can be tested by directly loading voltages to a first test pad and a second test pad after a first conductive layer is formed and before a first insulating layer is formed. After a second conductive layer is formed, a resistivity of the second test line is tested by loading voltages to a third test pad and a fourth test pad.

A semiconductor structure includes the following: a semiconductor substrate; a first metal layer, located on a surface of the semiconductor substrate; a second metal layer, located above a surface of the first metal layer; an insulating layer, located between the first metal layer and the second metal layer, and configured to isolate the first metal layer and the second metal layer; a test via, penetrating through the insulating layer and connecting the first metal layer with the second metal layer through a conductive material in the test via; and at least a pair of dummy vias, penetrating through the insulating layer and connected to any one of the first metal layer and the second metal layer.

A semiconductor structure includes: a semiconductor substrate; a first metal layer located on a surface of the semiconductor substrate; a second metal layer located above a surface of the first metal layer; an insulating layer located between the first metal layer and the second metal layer and configured to isolate the first metal layer from the second metal layer; and at least four vias located in the insulating layer and a conductive material for connecting the first metal layer and the second metal layer is filled in the at least four vias.

A display panel is provided. The display panel includes a plurality of signal lines and a testing circuit. The testing circuit includes a plurality of transistors electrically connected to the plurality of signal lines. The plurality of transistors are disposed in at least two groups, and a number of transistors of each group of the at least two groups is less than a total number of the plurality of signal lines. Therefore, the testing circuit of the display panel of the disclosure can reduce the circuit placement space in the horizontal direction.

Embodiments of the present disclosure relate to a monitoring circuit and a semiconductor device, and particularly, to a monitoring circuit including an oscillation circuit configured to generate an oscillation signal having a rising characteristic or a falling characteristic according to a threshold voltage level and a counter configured to count the number of rises or the number of falls of the oscillation signal, and a semiconductor device including the monitoring circuit.