Patent classifications
H01L2221/1073
FLEXIBLE AND STRETCHABLE INTERCONNECTS FOR FLEXIBLE SYSTEMS
A flexible device includes: (1) a flexible substrate; and (2) an interconnect disposed over the flexible substrate, wherein the interconnect has a varying vertical displacement along its length, relative to a top surface of the flexible substrate.
Metal contact structure and method of forming the same in a semiconductor device
A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.
Metal contact structure and method of forming the same in a semiconductor device
A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.
Method and apparatus for forming silicon oxide film on tungsten film
A method for forming a silicon oxide film on a tungsten film includes performing a first process of arranging an object to be processed in a processing container kept under a reduced pressure, the object including a tungsten film and a natural oxide film being formed on a surface of the tungsten film, performing a second process of forming a silicon seed layer by adsorbing a silicon-containing gas to the tungsten film, subsequently performing a third process of annealing the object and forming the silicon oxide film by a reaction of the natural oxide film and the silicon seed layer and subsequently performing a fourth process of forming an ALD silicon oxide film by ALD using a silicon-containing gas and an oxygen active species.
TREATMENT TO INTERFACE BETWEEN METAL FILM AND BARC OR PHOTORESIST
A method of manufacturing a semiconductor device is disclosed. In the method, a metallic layer is formed over a substrate, the metallic layer is surface-treated with an alkaline solution, and a bottom anti-reflective coating (BARC) layer is formed on the surface-treated metallic layer.
Metal Contact Structure and Method of Forming the Same in a Semiconductor Device
A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.
METHOD AND APPARATUS FOR FORMING SILICON OXIDE FILM ON TUNGSTEN FILM
A method for forming a silicon oxide film on a tungsten film includes performing a first process of arranging an object to be processed in a processing container kept under a reduced pressure, the object including a tungsten film and a natural oxide film being formed on a surface of the tungsten film, performing a second process of forming a silicon seed layer by adsorbing a silicon-containing gas to the tungsten film, subsequently performing a third process of annealing the object and forming the silicon oxide film by a reaction of the natural oxide film and the silicon seed layer and subsequently performing a fourth process of forming an ALD silicon oxide film by ALD using a silicon-containing gas and an oxygen active species.
Interconnect Structure That Avoids Insulating Layer Damage and Methods of Making the Same
A method for forming an interconnect structure includes forming an insulating layer on a substrate. A damascene opening is formed through a thickness portion of the insulating layer. A diffusion barrier layer is formed to line the damascene opening. A conductive layer is formed overlying the diffusion barrier layer to fill the damascene opening. A carbon-containing metal oxide layer is formed on the conductive layer and the insulating layer.
Package structure
Provided is a package structure including a die, an encapsulant, a through via, a first dielectric layer, a conductive line structure, an adhesion promotion layer, a second dielectric layer and a connector. The encapsulant is formed aside the die. The through via is formed aside the die and penetrates through the encapsulant. The first dielectric layer is formed overlying the die, the encapsulant and the through via. The conductive line structure includes a pad over the first dielectric layer. The adhesion promotion layer overlays a first portion of a top surface and a sidewall of the pad and overlying the first dielectric layer. The second dielectric layer overlays the adhesion promotion layer. The connector is in contact with a second portion of the top surface of the pad. The second portion of the top surface of the pad is exposed by the adhesion promotion layer.
METHOD FOR PRINTING AN ELECTRICALLY CONDUCTIVE LAYER ON A SURFACE OF 3D ELECTRONIC ASSEMBLY AND ASSOCIATED 3D ELECTRONIC ASSEMBLY
A method for depositing an electrically conductive layer on a surface of a three-dimensional (3D) electronic assembly comprising at least one electronic device embedded in a solid polymer material. The method comprises the steps of (i) providing a 3D electronic assembly, (ii) forming at least one flow barrier in the surface of the solid polymer material of the 3D electronic assembly, and (iii) depositing an electrically conductive layer on at least a portion of the surface of the solid polymer material, such that the electrically conductive layer is at least partially delimited by the flow barrier. The present invention also relates to an associated 3D electronic assembly.