A method is disclosed to form a metal-oxysilicate diffusion barrier for a damascene metallization. A trench is formed in an Inter Layer Dielectric (ILD) material. An oxysilicate formation-enhancement layer comprising silicon, carbon, oxygen, a constituent component of the ILD, or a combination thereof, is formed in the trench. A barrier seed layer is formed on the oxysilicate formation-enhancement layer comprising an elemental metal selected from a first group of elemental metals in combination with an elemental metal selected from a second group of elemental metals. An elemental metal in the second group is immiscible in copper or an alloy thereof, has a diffusion constant greater than a self-diffusion of copper or an alloy thereof; does not reducing silicon-oxygen bonds during oxysilicate formation; and promotes adhesion of copper or an alloy of copper to the metal-oxysilicate barrier diffusion layer. The structure is then annealed to form a metal-oxysilicate diffusion barrier.

The present disclosure provides a silicon film forming method for forming a silicon film on a workpiece having a processed surface, including: forming a seed layer by supplying a high-order aminosilane-based gas containing two or more silicon atoms in a molecular formula onto the processed surface and by having silicon adsorbed onto the processed surface; and forming a silicon film by supplying a silane-based gas not containing an amino group onto the seed layer and by depositing silicon onto the seed layer, wherein, when forming a seed layer, a process temperature is set within a range of 350 degrees C. or lower and a room temperature or higher.

Embodiments of the present disclosure are related to improved methods for forming an interconnect structure in a substrate. In one implementation, the method includes providing a substrate comprising a metal region and a dielectric region surrounding the metal region, selectively forming a cobalt-containing alloy cap layer on the metal region by exposing the substrate to a first precursor and a second precursor, the first precursor and the second precursor are selected from a group consisting of an aluminum-containing precursor, a cobalt-containing precursor, a ruthenium-containing precursor, a manganese-containing precursor, and a tungsten-containing precursor, wherein the first precursor is different from the second precursor.

The present application discloses a copper filled recess structure, which comprises a recess formed in a first dielectric layer; a block layer is formed on the bottom surface and side surfaces of the recess; a cobalt layer and a ruthenium layer are formed on the surface of the block layer; a copper layer completely fills the recess; a supportive nucleation film layer of the copper layer is formed by superposing the cobalt layer and the ruthenium layer. The present application further discloses a method for making a copper filled recess structure. Since the copper layer in the present application does not contain a copper seed layer and completely consists of the electrochemically-plated copper film, the ability of filling copper in the recess can be improved, and it is especially suitable for use as a copper connection and a via at a process node of less than 14 nm.

The present application discloses a contact, which comprises a contact opening, and a Ti layer, a glue layer and a tungsten layer which completely fill the contact opening; the Ti layer is subjected to annealing treatment; the tungsten layer comprises a tungsten seed layer and a tungsten body layer; the glue layer consists of a TiN layer which is divided into a plurality of TiN sub-layers, all or part of the TiN sub-layers are subjected to the annealing treatment, and the size of grains of the TiN sub-layer subjected to the annealing treatment is limited by the thickness of the corresponding TiN sub-layer. The present application further discloses a method for making a contact. The present application can prevent the annealing treatment of the TiSi layer from producing large lattice grains in the glue layer, thus can make the tungsten seed layer be a continuous structure.

A method of manufacturing a wafer assembly includes forming an array of planar wafer level metal posts extending from a surface of a substrate of a first wafer. After forming the array of posts, an oxide layer is applied over the surface of the first wafer and around the array of posts, the oxide layer being applied at a temperature of below 150 degrees Celsius.

Embodiments of the present disclosure are related to improved methods for forming an interconnect structure in a substrate. In one implementation, the method includes forming a barrier layer on exposed surfaces of a feature in a dielectric layer, forming a liner layer on the barrier layer, forming a seed layer on the liner layer, forming a metal fill on the seed layer by a metal fill process and overburdening the feature using an electroplating process, performing a planarization process to expose a top surface of the dielectric layer, and selectively forming a cobalt-aluminum alloy cap layer on the barrier layer, the liner layer, the seed layer, and the metal fill by exposing the substrate to a cobalt-containing precursor and an aluminum-containing precursor.

A method of forming a molybdenum-containing material on a substrate is described, in which the substrate is contacted with molybdenum oxytetrachloride (MoOCl.sub.4) vapor under vapor deposition conditions, to deposit the molybdenum-containing material on the substrate. In various implementations, a diborane contact of the substrate may be employed to establish favorable nucleation conditions for the subsequent bulk deposition of molybdenum, e.g., by chemical vapor deposition (CVD) techniques such as pulsed CVD.

An optoelectronic component and a method for producing an optoelectronic component are disclosed. In an embodiment an optoelectronic component includes a semiconductor layer sequence having an active region configured to emit radiation, a dielectric layer, a solder layer including a first metal arranged on the dielectric layer and a seed layer arranged between the solder layer and the dielectric layer, wherein the seed layer includes the first metal and a second metal, wherein the second metal is less noble than the first metal, wherein an amount of the second metal in the seed layer is between 0.5 wt % and 10 wt %, and wherein the first metal is Au and the second metal is Zn.

A method for fabricating a multi-layered wafer includes depositing a metal liner following by a seed layer including a metal in a trench arranged in an inter-metal dielectric (IMD). An end of the trench contacts a metal via of an interconnect structure. Heat is applied to drive the metal of the seed layer into the IMD and form a barrier layer along a sidewall of the trench.