Patent classifications
H01L2221/68377
APPARATUS FOR SEPARATING SEMICONDUCTOR CHIP AND METHOD FOR SEPARATING SEMICONDUCTOR BY USING SAME
Disclosed are an apparatus and a method for separating a semiconductor chip disposed on a base member via an adhesive member from the base member. The method includes: a step of providing a push member on a side of the base member opposite to a side on which the semiconductor chip is disposed and moving the push member in a direction adjacent to the semiconductor chip; and a step of separating the semiconductor chip, moved together with the push member, from the base member through a pick-up unit. The adhesive member and the push member are each magnetized such that repulsive forces act on each other.
Method of manufacturing a template wafer
A method for manufacturing a semiconductor device includes implanting gas ions in a donor wafer and bonding the donor wafer to a carrier wafer to form a compound wafer. The method also includes subjecting the compound wafer to a thermal treatment to cause separation along a delamination layer and growing an epitaxial layer on a portion of separated compound wafer to form a semiconductor device layer. The method further includes cutting the carrier wafer.
SUBSTRATE DIVIDING METHOD
A substrate dividing method includes preparing a substrate that is formed with division start points along streets and that has a protective sheet attached to a surface on one side thereof and rolling a roller on a surface on the other side of the substrate, to attach an expanding tape. Next, suction by a holding table is cancelled, and, in a state in which a slight gap is formed between a holding surface of the holding table and the protective sheet, the roller is brought into contact with the expanding tape and rolled, thereby extending cracks extending from the division start points while causing the substrate to sink into the gap through the protective sheet with the division start points as starting points, and the expanding tape is expanded to widen the chip intervals with the division start points as starting points.
Semiconductor package substrate and method of manufacturing semiconductor package using the same
Provided in a semiconductor package substrate including a semiconductor chip including a connection pad, an encapsulant encapsulating at least a portion of the semiconductor chip, a connection member disposed on the semiconductor chip and the encapsulant, the connection member including a redistribution layer that is electrically connected to the connection pad, a first passivation layer disposed on the connection member, and an adhesive layer disposed on at least one of a top surface of the encapsulant and a bottom surface of the first passivation layer in a region outside of the semiconductor chip.
APPARATUS AND METHODS FOR MICRO-TRANSFER-PRINTING
In an aspect, a system and method for assembling a semiconductor device on a receiving surface of a destination substrate is disclosed. In another aspect, a system and method for assembling a semiconductor device on a destination substrate with topographic features is disclosed. In another aspect, a gravity-assisted separation system and method for printing semiconductor device is disclosed. In another aspect, various features of a transfer device for printing semiconductor devices are disclosed.
SEMICONDUCTOR PACKAGE
A semiconductor package may include: a substrate; a first sub-semiconductor package disposed over the substrate, the first sub-semiconductor package including a first buffer chip and a first memory chip; and a second memory chip disposed over the first sub-semiconductor package, wherein the first buffer chip and the first memory chip are connected to each other using a first redistribution line, and wherein the first buffer chip and the second memory chip are connected to each other using a second bonding wire.
SEMICONDUTOR PACKAGE SUBSTRATE WITH DIE CAVITY AND REDISTRIBUTION LAYER
A semiconductor package includes a semiconductor substrate forming a cavity and a redistribution layer on a first side of the semiconductor substrate, the redistribution layer forming die contacts within the cavity and a set of terminals for the semiconductor package opposite the semiconductor substrate. The redistribution layer electrically connects one or more of the die contacts to the set of terminals. The semiconductor package further includes a semiconductor die including die terminals within the cavity with the die terminals electrically coupled to the die contacts within the cavity.
Chip transfer assembly and manufacturing method therefor, chip transfer method, and display backplane
A chip transfer assembly and a manufacturing method therefor, a chip transfer method, and a display backplane. The chip transfer assembly comprises a transfer substrate (1); a porous adhesive layer (2) formed on the transfer substrate, first pores (21) being distributed in the porous adhesive layer; and at least one colloid protrusions (3) formed on the porous adhesive layer, the colloid protrusions having light transmittance, and second pores (31) used for accommodating luminescent conversion particles (4) being distributed in the colloid protrusions; after an LED chip (7) is transferred to a chip soldering zone, the colloid protrusions separate from the porous adhesive layer and remain on the LED chip to form a luminescent conversion layer.
Packages With Multiple Types of Underfill and Method Forming The Same
A method includes bonding a first package component over a second package component, dispensing a first underfill between the first package component and the second package component, and bonding a third package component over the second package component. A second underfill is between the third package component and the second package component. The first underfill and the second underfill are different types of underfills.
Chip package and method of fabricating the same
A chip package including an integrated circuit component, a thermal conductive layer, an insulating encapsulant and a redistribution circuit structure is provided. The integrated circuit component includes an amorphous semiconductor portion located at a back surface thereof. The thermal conductive layer covers the amorphous semiconductor portion of the integrated circuit component, wherein thermal conductivity of the thermal conductive layer is greater than or substantially equal to 10 W/mK. The insulating encapsulant laterally encapsulates the integrated circuit component and the thermal conductive layer. The redistribution circuit structure is disposed on the insulating encapsulant and the integrated circuit component, wherein the redistribution circuit structure is electrically connected to the integrated circuit component.