The present invention provides a large die, a method of forming the large die and a large die wafer. The method includes: providing a wafer containing a plurality of large dies each having a size greater than that of a maximum field of exposure of a stepper, each large die including at least two die portions to be stitched together, the die portions including a substrate and a first metal layer, the first metal layer including at least to-be-interconnected metal layers for interconnection of the die portions; and forming a second metal layer including at least inter-die interconnecting metal layers crossing dummy dicing margins between adjacent die portions and coming into electrical connection with the to-be-interconnected metal layers of the adjacent die portions. The present invention allows interconnection of the die portions to be stitched together in each large die.

A recognition method for photolithography process and a semiconductor device are provided. The recognition method includes forming a mask layer on a semiconductor substrate, and then patterning the mask layer to form multiple dense line patterns in a cell region and multiple dummy dense line patterns in an interface region between the cell region and a peripheral region. At least one connection portion is provided between a first and a third dummy dense line patterns, and a second dummy dense line pattern is discontinuous at and separated from the at least one connection portion. A photoresist layer covering the peripheral region is formed on the semiconductor substrate, and whether a landing position of the photoresist layer is correct is determined according to a distance from an edge of the photoresist layer to a closest dummy dense line pattern and a width of the at least one connection portion.

A semiconductor structure that includes two circuit regions; two inner seal rings, each of the two inner seal rings surrounding one of the two circuit regions; an outer seal ring surrounding the two inner seal rings, wherein each of the inner seal rings and the outer seal ring has a substantially rectangular periphery with four interior corner seal ring structures; four first redundant regions between the two inner seal rings and the outer seal ring, each of the four first redundant regions being a substantially trapezoidal shape; and first dummy patterns substantially uniformly distributed in the four first redundant regions.

A template of one embodiment includes an alignment mark. The alignment mark includes a first main pattern and a first auxiliary pattern. In the first main pattern, a first part and a second part are disposed according to a predetermined repeating pattern. The first auxiliary pattern is configured as a pattern opposite to the repeating pattern in a region outside an end of the first main pattern.

A recognition method for photolithography process and a semiconductor device are provided. The recognition method includes forming a mask layer on a semiconductor substrate, and then patterning the mask layer to form multiple dense line patterns in a cell region and multiple dummy dense line patterns in an interface region between the cell region and a peripheral region. At least one connection portion is provided between a first and a third dummy dense line patterns, and a second dummy dense line pattern is discontinuous at and separated from the at least one connection portion. A photoresist layer covering the peripheral region is formed on the semiconductor substrate, and whether a landing position of the photoresist layer is correct is determined according to a distance from an edge of the photoresist layer to a closest dummy dense line pattern and a width of the at least one connection portion.

Substrate is produced by using a MEMS technique to form multiple diaphragms in a substrate by forming piezoelectric material layer on one surface of the substrate and thereafter by forming openings in the substrate from the other surface of the substrate; substrate and substrate on which signal detection circuit is formed are aligned to each other using at least one of multiple diaphragms as alignment diaphragm; and substrate and substrate are bonded together.

A semiconductor structure that includes two circuit regions; two inner seal rings, each of the two inner seal rings surrounding one of the two circuit regions; an outer seal ring surrounding the two inner seal rings, wherein each of the inner seal rings and the outer seal ring has a substantially rectangular periphery with four interior corner seal ring structures; four first redundant regions between the two inner seal rings and the outer seal ring, each of the four first redundant regions being a substantially trapezoidal shape; and first dummy patterns substantially uniformly distributed in the four first redundant regions.

In an embodiment, a semiconductor wafer includes a front surface, a plurality of active component positions, and at least one composite alignment mark arranged on the front surface and indicating a unique orientation of the semiconductor wafer. The composite alignment mark includes a first portion that has at least one raised section formed of a first material and a second portion that is positioned laterally adjacent the first portion. The second portion has at least one raised section formed of a second material that is different form the first material.

A semiconductor structure includes first and second inner seal rings each having a first section and a second section substantially perpendicular to the first section. The semiconductor structure further includes an outer seal ring. The outer seal ring has a third section, and a fourth section, and a fifth section. The semiconductor structure further includes dummy patterns substantially uniformly distributed in each of regions between the first inner seal ring and the outer seal ring and between the second inner seal ring and the outer seal ring.

A semiconductor package structure includes a first substrate, a second substrate, a pad layer and a conductive bonding layer. The first substrate has a first surface and a second surface opposite to the first surface. The second substrate has a first surface and a second surface opposite to the first surface. The second substrate is disposed side-by-side with the first substrate. The pad layer is disposed on the second surface of the first substrate and the second surface of the second substrate. The conductive bonding layer is disposed between the pad layer and the second surfaces of the first substrate and the second substrate.