The present application provides a method for preparing a semiconductor device, include the following steps: forming a source/drain (S/D) region in a semiconductor substrate; forming a bonding pad over the semiconductor substrate; forming a first spacer over a sidewall of the bonding pad; forming a first passivation layer covering the bonding pad and the first spacer; and forming a conductive bump over the first passivation layer, wherein the conductive bump penetrates through the first passivation layer to electrically connect to the bonding pad and the S/D region.

A semiconductor device includes first conductive films that are provided, above a semiconductor substrate, at least on both sides of a non-formation region in which the first conductive films are not provided; an interlayer dielectric film including a first portion that is provided on the non-formation region, second portions provided above the first conductive film on both sides of the non-formation region, and a step portion that connects the first portion and the second portions; a second conductive film provided above the interlayer dielectric film; through terminal portions that penetrate the second portions of the interlayer dielectric film; and a wire bonded with the second conductive film above the first portion, where the through terminal portions include one or more first through terminal portions and one or more second through terminal portions being provided at positions opposite to each other with a bonded portion of the wire being interposed therebetween.

A semiconductor device includes first conductive films that are provided, above a semiconductor substrate, at least on both sides of a non-formation region in which the first conductive films are not provided; an interlayer dielectric film including a first portion that is provided on the non-formation region, second portions provided above the first conductive film on both sides of the non-formation region, and a step portion that connects the first portion and the second portions; a second conductive film provided above the interlayer dielectric film; through terminal portions that penetrate the second portions of the interlayer dielectric film; and a wire bonded with the second conductive film above the first portion, where the through terminal portions include one or more first through terminal portions and one or more second through terminal portions being provided at positions opposite to each other with a bonded portion of the wire being interposed therebetween.

Provided is a substrate structure, including: a substrate body having a conductive contact; an insulating layer formed on the substrate body with the conductive contact exposed therefrom; and an insulating protection layer formed on a portion of a surface of the insulating layer, and having a plurality of openings corresponding to the conductive contact, wherein at least one of the openings is disposed at an outer periphery of the conductive contact. Accordingly, the insulating protection layer uses the openings to dissipate and disperse residual stresses in a manufacturing process of high operating temperatures.

In one embodiment, a semiconductor device includes one or more metallizations, such as, e.g., Cu-RDL metallizations, provided on a passivation layer over a dielectric layer. A via is provided through the passivation layer and the dielectric layer in the vicinity of the corners of the metallization. The via may be a “dummy” via without electrical connections to an active device and may be provided at a distance between approximately 1 micron (10.sup.−6 m.) and approximately 10 micron (10.sup.−5 m.) from each one of said converging sides landing on an underlying metal layer.

Manufacturing of flip-chip type assemblies is provided, and includes forming one or more contact elements of electrically conductive material on a carrier surface of at least one chip carrier, providing a restrain structure around the contact elements, depositing solder material on the contact elements and/or on one or more terminals of electrically conductive material on a chip surface of at least one integrated circuit chip, and placing the chip with each terminal facing corresponding contact elements. Further, the method includes soldering each terminal to the corresponding contact element by a soldering material, the soldering material being restrained during a soldering of the terminals to the contact elements by the restrain structure, and forming one or more heat dissipation elements of thermally conductive material on the carrier surface for facing the chip surface displaced from the terminals, where the one or more heat dissipation elements are free of any solder mask.

An embodiment is a device including an integrated circuit die having an active side and a back side, the back side being opposite the active side, a molding compound encapsulating the integrated circuit die, and a first redistribution structure overlying the integrated circuit die and the molding compound, the first redistribution structure including a first metallization pattern and a first dielectric layer, the first metallization pattern being electrically coupled to the active side of the integrated circuit die, at least a portion of the first metallization pattern forming an inductor.

Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a pad on a semiconductor chip, a protective layer on the semiconductor chip and having an opening that exposes a portion of a top surface of the pad, and a bump structure electrically connected to the pad. The bump structure includes a metal layer on the pad and a solder ball on the metal layer. A first width of the metal layer is about 0.85 times to about 0.95 times a second width of the opening.

A semiconductor component is provided. The semiconductor component includes a substrate and a pad. The pad has an upper surface and a slot, wherein the slot is recessed with respect to the upper surface.

An embodiment is a device including an integrated circuit die having an active side and a back side, the back side being opposite the active side, a molding compound encapsulating the integrated circuit die, and a first redistribution structure overlying the integrated circuit die and the molding compound, the first redistribution structure including a first metallization pattern and a first dielectric layer, the first metallization pattern being electrically coupled to the active side of the integrated circuit die, at least a portion of the first metallization pattern forming an inductor.