A fan-out semiconductor package module includes: a fan-out semiconductor package including a first interconnection member having a through-hole, a semiconductor chip disposed in the through-hole, an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip, a second interconnection member disposed on the first interconnection member and the semiconductor chip, a third interconnection member disposed on the encapsulant, first connection terminals disposed on the second interconnection member, and second connection terminals disposed on the third interconnection member, the first to third interconnection members including, respectively, redistribution layers electrically connected to connection pads of the semiconductor chip; and a component package stacked on the fan-out semiconductor package and including a wiring substrate connected to the second interconnection member through the first connection terminals and a plurality of mounted components mounted on the wiring substrate.

An electronic device includes a substrate, a first circuit, a plurality of bonding pads and a diode. The first circuit is disposed on the substrate. The bonding pads are disposed on the substrate, wherein at least one of the bonding pads is electrically connected to the first circuit through a bridge line. The diode is disposed on the substrate and electrically connected to the first circuit through at least one of the bonding pads. The bridge line crosses over a data line in a top view.

The present application discloses a method for fabricating a semiconductor device. The method includes providing a first chip comprising a first substrate, a first redistribution layer positioned above the first substrate, a first lower bonding pad positioned on the first redistribution layer, and a second lower bonding pad positioned above the first substrate and distant from the first lower bonding pad. The method also includes providing a second chip comprising a dense region and a loose region adjacent to the dense region; a plurality of upper pads positioned on the first lower bonding pad and the second lower bonding pad; and a plurality of second redistribution layers positioned on the plurality of upper pads. The method further performs bonding the second chip onto the first chip in a face-to-face manner, wherein the plurality of upper pads contact the first lower bonding pad and the second lower bonding pad.

The present application discloses a semiconductor device. The semiconductor device includes a first chip including a first substrate, a first redistribution layer above the first substrate, a first lower bonding pad positioned on the first redistribution layer, and a second lower bonding pad above the first substrate; and a second chip including a dense region and a loose region adjacent to the dense region, upper pads on the first lower bonding pad and the second lower bonding pad, second redistribution layers on the upper pads, and a first redistribution plug and a second redistribution plug respectively and correspondingly on the second redistribution layers. The first redistribution plug is at the dense region and includes a first aspect ratio. The second redistribution plug is at the loose region and includes a second aspect ratio less than the first aspect ratio.

Provided is a semiconductor integrated circuit device including a plurality of columns of IO cells and having a configuration capable of reducing wiring delays without causing an increase in the area. The semiconductor integrated circuit device includes a first IO cell column group including an IO cell column closest to a periphery of a chip, and a second IO cell column group including an IO cell column adjacent to the first IO cell column group at the side closer to the core region. At least one of the first IO cell column group or the second IO cell column group includes two or more IO cell columns, and the two or more IO cell columns are aligned in the second direction such that the lower power supply voltage regions face each other or the higher power supply voltage regions face each other.

Provided is a semiconductor integrated circuit device including a plurality of columns of IO cells and having a configuration capable of reducing wiring delays without causing an increase in the area. The semiconductor integrated circuit device includes a first IO cell column group including an IO cell column closest to a periphery of a chip, and a second IO cell column group including an IO cell column adjacent to the first IO cell column group at the side closer to the core region. At least one of the first IO cell column group or the second IO cell column group includes two or more IO cell columns, and the two or more IO cell columns are aligned in the second direction such that the lower power supply voltage regions face each other or the higher power supply voltage regions face each other.

A fan-out semiconductor package module includes: a fan-out semiconductor package including a first interconnection member having a through-hole, a semiconductor chip disposed in the through-hole, an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip, a second interconnection member disposed on the first interconnection member and the semiconductor chip, a third interconnection member disposed on the encapsulant, first connection terminals disposed on the second interconnection member, and second connection terminals disposed on the third interconnection member, the first to third interconnection members including, respectively, redistribution layers electrically connected to connection pads of the semiconductor chip; and a component package stacked on the fan-out semiconductor package and including a wiring substrate connected to the second interconnection member through the first connection terminals and a plurality of mounted components mounted on the wiring substrate.

A reconfigured semiconductor device includes a semiconductor device comprising an active surface having a plurality of input/output (I/O) pads spaced at a non-solderable pitch thereon and at least one redistribution layer overlying the active surface of the semiconductor device. Each at least one redistribution layer includes an insulating layer and a patterned conductive layer comprising a plurality of discrete terminal pads formed on the insulating layer, each of the plurality of discrete terminal pads electrically coupled to a respective I/O pad of the plurality of I/O pads by a conductive via formed through the insulating layer.

A reconfigured semiconductor device includes a semiconductor device comprising an active surface having a plurality of input/output (I/O) pads spaced at a non-solderable pitch thereon and at least one redistribution layer overlying the active surface of the semiconductor device. Each at least one redistribution layer includes an insulating layer and a patterned conductive layer comprising a plurality of discrete terminal pads formed on the insulating layer, each of the plurality of discrete terminal pads electrically coupled to a respective I/O pad of the plurality of I/O pads by a conductive via formed through the insulating layer.

A fan-out semiconductor package module includes: a fan-out semiconductor package including a first interconnection member having a through-hole, a semiconductor chip disposed in the through-hole, an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip, a second interconnection member disposed on the first interconnection member and the semiconductor chip, a third interconnection member disposed on the encapsulant, first connection terminals disposed on the second interconnection member, and second connection terminals disposed on the third interconnection member, the first to third interconnection members including, respectively, redistribution layers electrically connected to connection pads of the semiconductor chip; and a component package stacked on the fan-out semiconductor package and including a wiring substrate connected to the second interconnection member through the first connection terminals and a plurality of mounted components mounted on the wiring substrate.