A bonded structure is disclosed. The bonded structure can include an interconnect structure that has a first side and a second side opposite the first side. The bonded structure can also include a first die that is mounted to the first side of the interconnect structure. The first die can be directly bonded to the interconnect structure without an intervening adhesive. The bonded structure can also include a second die that is mounted to the first side of the interconnect structure. The bonded structure can further include an element that is mounted to the second side of the interconnect structure. The first die and the second die are electrically connected by way of at least the interconnect structure and the element.

A semiconductor device with small variations in high frequency characteristics by suppressing variations in impedance while maintaining high heat radiation is provided. The semiconductor device including a semiconductor package having two terminals, a wiring board having an opening at which the semiconductor package is positioned and having two electrodes connected to the two terminals and a heat sink fixing the semiconductor package in which a center of the semiconductor package is decentered with respect to a center of the opening is used. Also, the semiconductor device in which a center of the two electrodes is decentered from a center of the opening is used.

A semiconductor package includes a package substrate, an interposer above the package substrate, a connection terminal between the package substrate and the interposer, a first semiconductor chip and a second semiconductor chip above the interposer, a bridge in the interposer, the bridge connected to the first semiconductor chip and the second semiconductor chip, a capacitor structure in the interposer, the capacitor structure including an upper structure including an upper capacitor and a lower structure including a lower capacitor, and a chip connection terminal including at least one first chip connection terminal between the interposer and the first semiconductor chip and at least one second chip connection terminal between the interposer and the second semiconductor chip.

A chip package and method for fabricating the same are provided that include hybrid bonded bridge dies connecting IC dies on adjacent die stacks. In one example, a chip package includes an interconnect routing structure, a first die stack and a second die stack. The first die stack includes a top die disposed over a bottom die, the bottom die stacked on the interconnect routing structure. The second die stack also includes a top die disposed over a bottom die, the bottom die stacked on the interconnect routing structure. The first bridge die is electrically and mechanically coupled to the top dies of the first and second die stacks. The first bridge die having solid state circuitry that connects circuitries of the top dies of the first and second die stacks.

An embodiment provides a semiconductor package including: a first redistribution layer substrate; a semiconductor chip on the first redistribution layer substrate; a coupling member on the first redistribution layer substrate, wherein the coupling member is spaced apart from the semiconductor chip; an encapsulant on the first redistribution layer substrate, the semiconductor chip, and the coupling member; and a second redistribution layer substrate on the encapsulant, wherein the coupling member includes a vertical wire and a metal portion extending around the vertical wire, and wherein a first end of the coupling member is electrically connected to the first redistribution layer substrate, and a second end of the coupling member is electrically connected to the second redistribution layer substrate.

Disclosed are semiconductor packages and fabrication methods thereof. The semiconductor package includes a substrate, a first semiconductor chip and a second semiconductor chip that are mounted on the substrate, and a bridge chip between a first lateral surface of the first semiconductor chip and a second lateral surface of the second semiconductor chip. The first semiconductor chip and the second semiconductor chip are electrically connected through the bridge chip. The first semiconductor chip includes a first chip pad on the first lateral surface. The bridge chip includes a first connection pad on a first surface of the bridge chip. The first lateral surface of the first semiconductor chip and the first surface of the bridge chip are in contact with each other. The first chip pad and the first connection pad include a same material and are bonded to each other to constitute an integral piece formed.

An electronic component embedded substrate 1 includes a substrate 10 having a wiring layer 11 and an insulating layer 12; an electronic component 20 built in the substrate 10, and having a pair of electrode layers 21A and 21B, and a dielectric layer 22; and a stress relieving layer 30 provided closer to the wiring layer 11 than the insulating layer 12 is in the lamination direction, wherein at least part of an end portion of the electronic component 20 on the wiring layer 11 side is in contact with the stress relieving layer 30, wherein at least part of an end portion of the electronic component 20 on the insulating layer 12 side is in contact with the insulating layer 12, and wherein the Young's modulus of the stress relieving layer 30 is lower than the Young's modulus of the electrode layer 21B.

A semiconductor package includes a package substrate, an interposer on the package substrate and including first upper pads, the first upper pads including a first set of upper pads and a second set of upper pads, a first semiconductor chip on the interposer and comprising first lower pads respectively connected to the first set of upper pads, a plurality of first pins on a first top surface of the first semiconductor chip and substantially uniformly spaced apart by a first distance, and a plurality of second pins on the first top surface of the first semiconductor chip and substantially uniformly spaced apart by a second distance that is different from the first distance, where the first top surface of the first semiconductor chip includes a first region and a second region that does not overlap the first region.

Provided is a semiconductor package including a printed circuit board including a cavity extending inward from an upper surface thereof, an optical waveguide extending onto the cavity along the upper surface of the printed circuit board, a first semiconductor chip positioned inside the cavity and including a photonic integrated circuit overlapping a portion of the optical waveguide in a vertical direction, an interposer on the first semiconductor chip, and a second semiconductor chip on the interposer.

Apparatuses include a package substrate with package bonding pads and a die electrically coupled to the package substrate via conductive bonding elements. The die includes a first application-specific integrated circuit (ASIC) with first die input/output pads and a second ASIC with second die input/output pads. Each of the first die input/output pads is electrically coupled to at least one corresponding package bonding pad. At least one of the second die input/output pads is not electrically coupled to any package bonding pad, such that the second ASIC is left in an inoperable state.