A semiconductor package includes a package substrate, a logic chip stacked on the package substrate and including at least one logic element, and a stack structure. The stack structure includes an integrated voltage regulator (IVR) chip including a voltage regulating circuit that regulates a voltage of the at least one logic element, and a passive element chip stacked on the IVR chip and including an inductor.

Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes an integrated circuit structure, a first die stack and a dummy die. The first die stack includes a plurality of first die structures and is bonded to the integrated circuit structure at a first side of the first die stack. The dummy die includes a plurality of through substrate vias, is located aside the first die stack and is electrically connected to the integrated circuit structure at the first side of the first die stack. In some embodiments, the height of the through substrate vias of the dummy die is the same as the height of the first die stack.

A semiconductor package includes a package substrate, a logic chip stacked on the package substrate and including at least one logic element, and a stack structure. The stack structure includes an integrated voltage regulator (IVR) chip including a voltage regulating circuit that regulates a voltage of the at least one logic element, and a passive element chip stacked on the IVR chip and including an inductor.

Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes an integrated circuit structure, a first die stack and a dummy die. The first die stack includes a plurality of first die structures and is bonded to the integrated circuit structure at a first side of the first die stack. The dummy die includes a plurality of through substrate vias, is located aside the first die stack and is electrically connected to the integrated circuit structure at the first side of the first die stack. In some embodiments, the height of the through substrate vias of the dummy die is the same as the height of the first die stack.

A chip package includes a first chip and a second chip. The first chip includes a first substrate having a first surface and a second surface opposite to the first surface, a first passive element on the first surface, and a first protection layer covering the first passive element, which the first protection layer has a third surface opposite to the first surface. First and second conductive pad structures are disposed in the first protection layer and electrically connected to the first passive element. The second chip is disposed on the third surface, which the second chip includes an active element and a second passive element electrically connected to the active element. The active element is electrically connected to the first conductive pad structure.

An embodiment is a method including forming a first passive device in a first wafer, forming a first dielectric layer over a first side of the first wafer, forming a first plurality of bond pads in the first dielectric layer, planarizing the first dielectric layer and the first plurality of bond pads to level top surfaces of the first dielectric layer and the first plurality of bond pads with each other, hybrid bonding a first device die to the first dielectric layer and at least some of the first plurality of bond pads, and encapsulating the first device die in a first encapsulant.

An embodiment is a method including forming a first passive device in a first wafer, forming a first dielectric layer over a first side of the first wafer, forming a first plurality of bond pads in the first dielectric layer, planarizing the first dielectric layer and the first plurality of bond pads to level top surfaces of the first dielectric layer and the first plurality of bond pads with each other, hybrid bonding a first device die to the first dielectric layer and at least some of the first plurality of bond pads, and encapsulating the first device die in a first encapsulant.

Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes an integrated circuit structure, a first die stack and a dummy die. The first die stack includes a plurality of first die structures and is bonded to the integrated circuit structure at a first side of the first die stack. The dummy die includes a plurality of through substrate vias, is located aside the first die stack and is electrically connected to the integrated circuit structure at the first side of the first die stack. In some embodiments, the height of the through substrate vias of the dummy die is the same as the height of the first die stack.

An integrated circuit package includes a substrate, a flip chip die, and a capacitor. The flip chip die is attached to the substrate via die-to-substrate interconnects. The capacitor is attached to the flip chip die via capacitor-to-die interconnects so that the capacitor occupies a region between the flip chip die and the substrate. Such placement of the capacitor on a flip chip die has the advantage of reducing the distance between the capacitor and its core, thereby reducing unwanted line inductance and series resistance effects. Integrated circuit performance is thereby enhanced.

A circuit assembly includes an integrated circuit (IC) die and a first capacitor die. The IC die provides an IC and includes a plurality of first conductive pads. The first capacitor die provides a plurality of capacitors, and includes a plurality of second conductive pads at the first side and a plurality of conductive vias at the second side. At least one of the second conductive pads electrically connects to the capacitors. The conductive vias is adapted to form a plurality of external signal connections of the IC die and the first capacitor die. The IC die is stacked with the first capacitor die in such a way that the first conductive pads electrically connect to the second conductive pads, and surfaces of the IC die and the first capacitor die attaching to each other are substantially of the same size.