A semiconductor device has a semiconductor die with a die pad layout. Signal pads in the die pad layout are located primarily near a perimeter of the semiconductor die, and power pads and ground pads are located primarily inboard from the signal pads. The signal pads are arranged in a peripheral row or in a peripheral array generally parallel to an edge of the semiconductor die. Bumps are formed over the signal pads, power pads, and ground pads. The bumps can have a fusible portion and non-fusible portion. Conductive traces with interconnect sites are formed over a substrate. The bumps are wider than the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

Apparatus and methods for electrical overstress (EOS) protection circuits are provided herein. In certain configurations, an EOS protection circuit includes an overstress sensing circuit electrically connected between a pad and a first supply node, an impedance element electrically connected between the pad and a signal node, a controllable clamp electrically connected between the signal node and the first supply node and selectively activatable by the overstress sensing circuit, and an overshoot limiting circuit electrically connected between the signal node and a second supply node. The overstress sensing circuit activates the controllable clamp when an EOS event is detected at the pad. Thus, the EOS protection circuit is arranged to divert charge associated with the EOS event away from the signal node to provide EOS protection.

A semiconductor package may include a package substrate, a first semiconductor chip on the package substrate, and a second semiconductor chip on the first semiconductor chip. The first semiconductor chip comprises a chip substrate including a first surface and a second surface opposite to the first surface, a plurality of first chip pads between the package substrate and the chip substrate, and electrically connecting the first semiconductor chip to the package substrate, a plurality of second chip pads disposed on the second surface and between the second semiconductor chip and the second surface, and a plurality of redistribution lines on the second surface, the redistribution lines electrically connecting to the second semiconductor chip, and a plurality of bonding wires electrically connecting the redistribution lines to the package substrate.

Disclosed are a chip on film (COF) and a display device including the same, for reducing the number of input pads using a pattern branching structure. The COF is connected to gate-in-panel (GIP) output pads using a structure formed via branching of GIP wirings connected to the GIP input pads in a data driving integrated circuit (IC) or a circuit film to reduce the number of GIP input pads.

A fan-out semiconductor package includes: a core member having a first through-hole and including first and second wiring layer disposed on different levels; a first semiconductor chip disposed in the first through-hole; a second semiconductor chip disposed on the first semiconductor chip in the first through-hole so that a second inactive surface faces a first inactive surface; conductive wires disposed on the core member and a second active surface and electrically connecting second connection pads and the second wiring layer to each other; an encapsulant covering at least portions of the core member, the first semiconductor chip, the second semiconductor chip, and the conductive wires and filling at least portions of the first through-hole; and a connection member disposed on the core member and a first active surface and electrically connecting first connection pads and the first wiring layer to each other.

A semiconductor package may include a package substrate, a first semiconductor chip on the package substrate, and a second semiconductor chip on the first semiconductor chip. The first semiconductor chip comprises a chip substrate including a first surface and a second surface opposite to the first surface, a plurality of first chip pads between the package substrate and the chip substrate, and electrically connecting the first semiconductor chip to the package substrate, a plurality of second chip pads disposed on the second surface and between the second semiconductor chip and the second surface, and a plurality of redistribution lines on the second surface, the redistribution lines electrically connecting to the second semiconductor chip, and a plurality of bonding wires electrically connecting the redistribution lines to the package substrate.

A fan-out semiconductor package includes: a core member having a first through-hole and including first and second wiring layer disposed on different levels; a first semiconductor chip disposed in the first through-hole; a second semiconductor chip disposed on the first semiconductor chip in the first through-hole so that a second inactive surface faces a first inactive surface; conductive wires disposed on the core member and a second active surface and electrically connecting second connection pads and the second wiring layer to each other; an encapsulant covering at least portions of the core member, the first semiconductor chip, the second semiconductor chip, and the conductive wires and filling at least portions of the first through-hole; and a connection member disposed on the core member and a first active surface and electrically connecting first connection pads and the first wiring layer to each other.

Disclosed are a chip on film (COF) and a display device including the same, for reducing the number of input pads using a pattern branching structure. The COF is connected to gate-in-panel (GIP) output pads using a structure formed via branching of GIP wirings connected to the GIP input pads in a data driving integrated circuit (IC) or a circuit film to reduce the number of GIP input pads.

A semiconductor device has an interposer and a surface mount technology (SMT) component disposed on the interposer. The interposer is disposed on an active surface of a semiconductor die. The semiconductor die is disposed on a substrate. A first wire bond connection is formed between the interposer and semiconductor die. A second wire bond connection is formed between the interposer and substrate. A third wire bond connection is formed between the substrate and semiconductor die. An encapsulant is deposited over the substrate, semiconductor die, interposer, and SMT component. In one embodiment, the substrate is a quad flat non-leaded substrate. In another embodiment, the substrate is a land-grid array substrate, ball-grid array substrate, or leadframe.

Apparatus and methods for electrical overstress (EOS) protection circuits are provided herein. In certain configurations, an EOS protection circuit includes an overstress sensing circuit electrically connected between a pad and a first supply node, an impedance element electrically connected between the pad and a signal node, a controllable clamp electrically connected between the signal node and the first supply node and selectively activatable by the overstress sensing circuit, and an overshoot limiting circuit electrically connected between the signal node and a second supply node. The overstress sensing circuit activates the controllable clamp when an EOS event is detected at the pad. Thus, the EOS protection circuit is arranged to divert charge associated with the EOS event away from the signal node to provide EOS protection.