An electronic-part-reinforcing thermosetting resin composition has: a viscosity of 5 Pa.Math.s or less at 140° C.; a temperature of 150° C. to 170° C. as a temperature corresponding to a maximum peak of an exothermic curve representing a curing reaction; and a difference of 20° C. or less between the temperature corresponding to the maximum peak and a temperature corresponding to one half of the height of the maximum peak in a temperature rising range of the exothermic curve.

A semiconductor package capable of reducing or preventing cracks from occurring in a conductive bump and a method for manufacturing the same. The semiconductor package includes a semiconductor chip; a first conductive bump; a first re-distribution layer which is provided between the semiconductor chip and the first conductive bump and electrically connects the semiconductor chip and the first conductive bump; and a buffer structure which formed to fill up a space between a side surface of the first conductive bump and one surface of the first re-distribution layer, in which the buffer structure includes a plurality of pores.

A mounting structure includes a bonding material (106) that bonds second electrodes (104) of a circuit board (105) and bumps (103) of a semiconductor package (101), the bonding material (106) being surrounded by a first reinforcing resin (107). Moreover, a portion between the outer periphery of the semiconductor package (101) and the circuit board (105) is covered with a second reinforcing resin (108). Even if the bonding material (106) is a solder material having a lower melting point than a conventional bonding material, high drop resistance is obtained.

A reinforcing resin composition includes an epoxy resin (A), a phenolic resin (B), and a benzoxazine compound (C).

A method of manufacturing a semiconductor package including coating a flux on a connection pad provided on a first surface of a substrate, the flux including carbon nanotubes (CNTs), placing a solder ball on the connection pad coated with the flux, forming a solder layer attached to the connection pad from the solder ball through a reflow process, and mounting a semiconductor chip on the substrate such that the solder layer faces a connection pad in the semiconductor chip may be provided.

Manufacturing of flip-chip type assemblies is provided, and includes forming one or more contact elements of electrically conductive material on a carrier surface of at least one chip carrier, providing a restrain structure around the contact elements, depositing solder material on the contact elements and/or on one or more terminals of electrically conductive material on a chip surface of at least one integrated circuit chip, and placing the chip with each terminal facing corresponding contact elements. Further, the method includes soldering each terminal to the corresponding contact element by a soldering material, the soldering material being restrained during a soldering of the terminals to the contact elements by the restrain structure, and forming one or more heat dissipation elements of thermally conductive material on the carrier surface for facing the chip surface displaced from the terminals, where the one or more heat dissipation elements are free of any solder mask.

A wiring board includes first insulating layers; first wiring layers; first via wirings; second insulating layers; second wiring layers; second via wirings; and a solder resist layer, wherein the first insulating layers are composed of non-photosensitive resin, wherein the second insulating layers, and the solder resist layer are composed of photosensitive resin, respectively, wherein the first surface of the uppermost first insulating layer and the first end surface of the first via wiring embedded in the uppermost first insulating layer are polished surfaces, wherein the first end surface of the first via wiring embedded in the uppermost first insulating layer is flush with the first surface of the uppermost first insulating layer, and wherein the wiring density of the second wiring layers is higher than the wiring density of the first wiring layers.

The present disclosure provides an electronic device. The electronic device includes a first resin layer, having a first resin layer main surface and a first resin layer inner surface; a first conductor, having a first conductor main surface and a first conductor inner surface; a first wiring layer, formed adjacent to the first resin layer main surface and connected to the first conductor main surface; a first electronic component, electrically connected with the first wiring layer; a second resin layer, having a second resin layer main surface facing same direction as the first resin layer main surface and a second resin layer inner surface being in contact with the first resin layer main surface; an external electrode; and a second conductor, penetrating the second resin layer, wherein the second conductor is disposed on a periphery of the first electronic component.

An electronic device includes: a first resin layer having a first resin layer main surface and a first resin layer inner surface; a columnar conductor having a columnar conductor main surface and a columnar conductor inner surface and penetrating the first resin layer in direction z; a wiring layer connecting the first resin layer main surface and the first conductor main surface; an electronic component being electrically connected and joined to the wiring layer; a second resin layer having a second resin layer main surface facing the same direction as the first resin layer main surface and a second resin layer inner surface being in contact with the first resin layer main surface, covering the wiring layer and the electronic component; and an external electrode closer to the side where the first resin layer inner surface faces than the first resin layer and is electrically connected to the columnar conductor.

Packaging methods for semiconductor devices and methods of packaging thereof are disclosed. In some embodiments, a device includes a packaging apparatus and contact pads disposed on the packaging apparatus. The contact pads are arranged in an array of rows and columns. The contact pads include first contact pads proximate a perimeter region of the packaging apparatus and second contact pads disposed in an interior region of the packaging apparatus. A dam structure that is continuous is disposed around the second contact pads. The contact pads comprise a mounting region for a semiconductor device.